Senior DSP/PHY Engineer — Space Communications & ASIC

Blue Origin LLC; San Francisco (CA); Hybrid; USD 230,000 - 323,000; Full time

Benefits offered by this job

Medical, dental, vision

Stock options

Paid time off

Job summary

Blue Origin seeks a senior signal processing engineer to lead DSP/PHY algorithm development for the TeraWave Custom Silicon. You will model, implement, and optimize algorithms in MATLAB/Python/C/C++ for DSP and communications, with emphasis on fixed‑point precision, bit‑accurate verification, and low‑power designs.

You will collaborate with ASIC, RFIC, and SW teams, drive pre‑silicon and post‑silicon validation, and mentor junior engineers while targeting FPGA and ASIC implementations for

Qualifications

• 10+ years of experience in signal processing or modem design.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Strong hands-on programming in MATLAB, Python, and C/C++ for DSP/communications algorithms.

Responsibilities

• Develop models and algorithms for the TeraWave Custom Silicon.
• Implement DSP/PHY algorithms using MATLAB, Python, and C/C++.
• Optimize for low power and high performance across FPGA and ASIC implementations.
• Support pre-silicon verification and post-silicon validation across models, RTL/FPGA, and silicon.
• Collaborate with ASIC, RFIC, and SW teams to bring up prototypes.
• Drive word-length analysis and fixed-point optimization for accuracy.
• Mentor junior engineers and contribute to design reviews.

Skills

Signal processing

Modem design

MATLAB

Python

C/C++

DSP

FPGA

ASIC

Beamforming

PHY

Education

Bachelor's degree in Electrical or Computer Engineering

MS/PhD in Electrical Engineering or related field

Tools

MATLAB

SystemC

C/C++

Python

Job description

Blue Origin seeks a senior signal processing engineer to lead DSP/PHY algorithm development for the TeraWave Custom Silicon. You will model, implement, and optimize algorithms in MATLAB/Python/C/C++ for DSP and communications, with emphasis on fixed‑point precision, bit‑accurate verification, and low‑power designs.

You will collaborate with ASIC, RFIC, and SW teams, drive pre‑silicon and post‑silicon validation, and mentor junior engineers while targeting FPGA and ASIC implementations for