Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer, Next-genera[...]

Micron Technology, Inc; Richardson (TX); On-site; USD 140,000 - 200,000; Full time

Job summary

Micron Technology, Inc in the United States is seeking a senior DRAM circuit design engineer to identify and develop novel memory architectures, validate them with SPICE simulations, and collaborate with layout teams on floorplanning and test strategies.

Ideal candidates have 8+ years in DRAM design, experience with HBM or stacked memories, and proficiency in Verilog and Python; a Master's or PhD in EE/CS is preferred. This role offers impactful work on AI memory systems.

Qualifications

• Strong mixed-signal design experience, including analog and synthesis flows.
• DRAM circuit design experience in cell arrays, sense amps, decoders, IO, or power distribution.
• Proficient with SPICE-based tools (e.g., FineSim, HSPICE) and data-driven analysis.
• Excellent communication to influence peers.

Responsibilities

• Identify and develop novel DRAM circuit architectures to improve bandwidth and energy efficiency.
• Collaborate to identify bottlenecks and define architectural hypotheses.
• Validate hypotheses via schematic-level design, SPICE, and trade-off analysis.
• Partner with layout designers to conduct floorplanning studies.
• Define and optimize design-for-test and design-for-yield implementations.
• Compose and maintain clear specifications and architecture documentation.

Skills

Mixed-signal design

DRAM circuit design

Cell arrays

Sense amplifiers

Row/Column decoders

Periphery

IO

Power distribution

Communication skills

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering or related field

Tools

SPICE (FineSim, HSPICE)

Verilog

Python

Perl

Job description

Micron Technology is a world leader in innovating memory and storage solutions. We are building next‑generation, high‑bandwidth memory products for emerging AI systems and applications.

Responsibilities

• Identify and develop novel DRAM circuit architectures that anticipate next‑generation AI workload requirements to unlock improvements in bandwidth and energy efficiency.
• Collaborate with peers to identify the highest‑leverage DRAM circuit bottlenecks and define architectural hypotheses.
• Validate architectural hypotheses through schematic‑level circuit design, SPICE simulation, and trade‑off analysis, establishing PPA feasibility.
• Partner with layout designers to conduct floorplanning studies.
• Collaboratively define and optimize design‑for‑test, design‑for‑yield implementation.
• Compose and maintain clear specifications and architecture documentation.

Minimum Qualifications

• Strong mixed‑signal design experience, including experience with custom analog and synthesis flows.
• DRAM circuit design experience in one or more of the following focus areas: cell arrays, sense amplifiers, row/column decoders, periphery, IO, and/or power distribution.
• Engineering experience with SPICE‑based tools (e.g., FineSim, HSPICE).
• Strong communication skills with an ability to influence others through deeply technical, data‑driven analysis.

Preferred Qualifications

• Experience with HBM or other novel stacked memory architectures.
• Experience in one or more scripting languages (e.g., Python, Perl) and hardware description language (e.g., Verilog).
• Strong knowledge of semiconductor device physics.
• A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
• 8+ years of proven experience delivering DRAM‑based memory designs.

Job Profile(s)

• Systems Design Engineering SMTS

Relocation Level

TBD

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.