Senior Digital Verification Engineer - SerDes IP

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in California is seeking a Senior Digital Design Verification Engineer to verify the design and implementation of SerDes IPs used in high‑speed interfaces for gaming and AI. Join a best‑in‑class team delivering validated IPs across standard and proprietary protocols.

You will develop test plans, create reusable verification components in SystemVerilog/UVM, and collaborate with architects, designers, and cross‑functional teams to meet product schedules.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering.
• At least 5 years of verified experience in digital design verification.
• Background in unit/sub-system/SOC level verification and SystemVerilog expertise.
• Experience with random stimulus, functional coverage, and assertion-based verification.
• Experience with UVM/VMM and industry verification tools.

Responsibilities

• Verify digital design, golden models, and micro-architecture of SerDes IPs using UVM.
• Build reusable verification components, monitors, checkers and scoreboards with coverage-driven methodology.
• Define verification scope, develop infrastructure, and verify design correctness for product shipments.
• Write and implement test plans and thoroughly verify designs under tight schedules.
• Collaborate with architects, designers, and cross‑functional verification teams.

Skills

SystemVerilog

UVM

C/C++

Python

Perl

Debugging

Teamwork

Education

Bachelor's or Master's in EE/CS/CE

Job description

NVIDIA Corporation in California is seeking a Senior Digital Design Verification Engineer to verify the design and implementation of SerDes IPs used in high‑speed interfaces for gaming and AI. Join a best‑in‑class team delivering validated IPs across standard and proprietary protocols.

You will develop test plans, create reusable verification components in SystemVerilog/UVM, and collaborate with architects, designers, and cross‑functional teams to meet product schedules.