Senior Digital Design Verification Engineer - Hardware

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 136,000 - 218,500; Full time

Job summary

NVIDIA Gruppe seeks a Senior Digital Design Verification Engineer in Santa Clara, California, to verify cutting-edge SerDes IPs contributing to AI and gaming. The ideal candidate will have extensive experience with digital design verification and must possess a Bachelor's or Master's degree in a relevant field.

The role involves using advanced methodologies like UVM and collaborating with architecture and design teams. A competitive salary and equity are offered, reflecting a commitment to diversity and equality.

Qualifications

• Minimum of 5 years validated experience in digital design verification.
• Background in verification methodologies and tools essential.
• Experience in verifying complex SerDes systems and mixed-signal designs.

Responsibilities

• Verification of the digital design and micro-architecture of SerDes IPs.
• Developing verification infrastructure and correctness of design.
• Writing and implementing test plans with a focus on product shipment.

Skills

Verification of the digital design

Strong interpersonal skills

Good debugging and analytical skills

Expertise in SystemVerilog

Experience in UVM

Education

Bachelor's or Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering

Tools

SystemVerilog

UVM

Perl

Python

C/C++

Job description

As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify the design and implementation of our cutting‑edge SerDes IPs. This groundbreaking technology will enable and accelerate gaming, artificial intelligence, deep learning, and autonomous driving. We have put together a best‑in‑class team that delivers IPs that will be consumed by standard as well as industry‑leading proprietary high‑speed protocols!

What you’ll be doing:

• Verification of the digital design, golden models and micro‑architecture of the SerDes IPs using advanced verification methodologies such as UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Responsible for understanding the design and implementation, defining the verification scope, developing the verification infrastructure and verifying the correctness of the design.
• Write and implement test plan and thoroughly verify a design in a product shipment focused/compressed schedule.
• Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

What we need to see:

• Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering.
• At least 5 years of validated experience.
• Background in verification at Unit/Sub‑system/SOC level and expertise in SystemVerilog a must.
• Experience using random stimulus along with functional coverage and assertion‑based verification methodologies a must.
• Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.

Ways to stand out from the crowd:

• Expertise in bus or interconnect protocols (e.g. PCI Express, USB, SATA) a huge plus.
• Experience in verifying complex SerDes system, understanding mixed‑signal designs, and have experience in modeling of analog circuits a huge plus.
• Perl, Python, C/C++ programming language experience.
• Good debugging and analytical skills.
• Good interpersonal skills & dream to work as a phenomenal teammate.

Salary and Benefits

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $136,000 USD - $218,500 USD for Level 3, and $168,000 USD - $264,500 USD for Level 4. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.