Senior Digital Design Manager — Mixed-Signal Silicon Leader

NVIDIA Corporation; Santa Clara (CA); On-site; USD 196,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a Senior Digital Design Manager to lead a high-performance mixed-signal/ digital design group in Santa Clara. You will drive teams developing cutting-edge SerDes IPs and SoCs, focusing on PPA optimization and robust verification.

The role demands 8+ years in mixed-signal design with strong leadership, Verilog/SystemVerilog proficiency, and experience with Ethernet/PCIe protocols. Equity and comprehensive benefits accompany the base salary.

Qualifications

• MS or PhD in Electrical Engineering or equivalent experience.
• 3+ years in leadership of mixed-signal/ digital design teams.
• Strong background in Verilog/SystemVerilog and RTL for mixed-signal blocks.

Responsibilities

• Lead and mentor a team of engineers in developing mixed-signal chips.
• Oversee planning and specification of algorithms, evaluating PPA trade-offs.
• Guide design of digital circuits such as filters and analog calibration circuits.
• Ensure verification of digital designs using direct and random testing methodologies.
• Lead front-end design flows (Lint/CDC/Synthesis/DFT/LEC/STA) and coordinate with back-end teams for chip tape-outs.
• Drive silicon bring-up and performance optimization.
• Collaborate with multi-functional teams to align roadmaps with business objectives.
• Establish and maintain standard methodologies for mixed-signal design and verification.

Skills

Leadership

Verilog/SystemVerilog

RTL design

UVM

Static timing

Formal verification

Communication

Education

MS or PhD in Electrical Engineering

Tools

UVM

RTL modeling

Job description

NVIDIA Corporation is seeking a Senior Digital Design Manager to lead a high-performance mixed-signal/ digital design group in Santa Clara. You will drive teams developing cutting-edge SerDes IPs and SoCs, focusing on PPA optimization and robust verification.

The role demands 8+ years in mixed-signal design with strong leadership, Verilog/SystemVerilog proficiency, and experience with Ethernet/PCIe protocols. Equity and comprehensive benefits accompany the base salary.