Staff Digital Design Engineer

OMNIVISION; Town of Norway (WI); On-site; USD 90,000 - 120,000; Full time

Job summary

OMNIVISION is searching for a skilled digital design engineer to handle responsibilities in the design and verification of digital IP for CIS, define architecture, and mentor junior team members. A minimum MSEE and 7+ years of digital design experience are required, along with expertise in RTL design for ASICs. Candidates should have strong collaboration skills and possibly technical lead experience. This role offers a dynamic environment and opportunities for innovation and improvement in design processes.

Qualifications

• Minimum MSEE + at least 7 years of digital design experience.
• Expertise in RTL design and verification for ASICs.
• Ability to work collaboratively with cross-functional teams.

Responsibilities

• Design and verification of digital IP for CIS.
• Define chip level architecture considering power, performance & area trade-offs.
• Drive innovation and continuous improvement of design flow.
• Silicon bring-up, validation, and debug.

Skills

RTL design and verification for ASICs

Digital design experience

Collaboration skills

Static timing analysis

Image processing/DSP knowledge

Education

MSEE

Job description

Responsibilities

• Design and verification of digital IP for CIS
• Define chip level architecture taking into consideration power, performance & area trade-offs; build top level and module specification
• Perform logic synthesis, work with backend team for floor planning, STA and DFT
• Drive innovation and continuous improvement of design flow
• Mentor junior team members
• Participate in project planning and progress tracking
• Full-chip integration and verification
• Silicon bring-up, validation and debug

Qualifications

• Minimum MSEE + at least 7 yrs. of digital design experience
• Expertise in RTL design and verification for ASICs.
• Experience handling logic synthesis and static timing analysis for multiple projects
• Knowledge of all aspects of chip development cycle from design specification, architecture definition, low-power design, tape-out, to chip validation and debug
• Technical lead experience is a plus
• Knowledge of ASIL is a plus
• Knowledge of DFT is a plus
• Image processing/DSP knowledge is a plus
• Excellent command of English as a working language is a must
• Ability to work collaboratively with people across multiple functional areas