Senior Digital Design Lead - Automation & Verification

SmartRecruiters, Inc.; Austin (TX); On-site; USD 130,000 - 200,000; Full time

Job summary

Renesas Electronics in Austin seeks a senior digital design engineer to develop, debug and verify complex digital blocks across pre and post-silicon environments. You will write verification tests, automate design flows, and mentor junior engineers within a collaborative team.

The role emphasizes leadership, strong debugging skills, and familiarity with Cadence or Synopsys tool flows, as well as effective communication across teams.

Qualifications

• BSc/MSc in Electrical Engineering/Computer Engineering (EE/ECE) and 10+ years of relevant industry experience.
• Prior design project work experience showing collaborative and innovative thinking.
• Comfortable with debugging mixed-signal designs in System Verilog based test benches.
• Exposed to gate level simulation debug.
• Strong analytical skills and debug methodology.
• Good written and verbal communications skills.
• Working experience with Cadence or Synopsys design tool flows.
• Hands-on technical leadership role resulting in successful projects.

Responsibilities

• Develop, debug, and verify digital designs in pre and post silicon environment.
• Write tests to verify bulk design intent as per specification.
• Learn, develop and improve scripts to facilitate design automation flows.
• Manage assigned design blocks in design requirements, architecture, and implementation.
• Research and present new tools in aid of design development process.
• Act as technical mentor for junior engineers.
• Represent digital design as functional digital design lead in design projects.

Skills

Technical leadership

Analytical skills

Communication skills

Debugging mixed-signal designs

Gate-level simulation debug

Collaboration

Education

BSc/MSc in EE/ECE

Tools

Cadence

Synopsys

Job description

Renesas Electronics in Austin seeks a senior digital design engineer to develop, debug and verify complex digital blocks across pre and post-silicon environments. You will write verification tests, automate design flows, and mentor junior engineers within a collaborative team.

The role emphasizes leadership, strong debugging skills, and familiarity with Cadence or Synopsys tool flows, as well as effective communication across teams.