Head of Digital Design & Verification Strategy

Renesas Electronics Corp.; Chandler (AZ); On-site; USD 180,000 - 240,000; Full time

Job summary

Renesas Electronics seeks a senior leader to define and execute world-class digital design and verification at our Chandler site. You will own end-to-end delivery, establish verification strategy across simulation, formal, and AMS/DMS, and drive architecture quality from system control logic to IP reuse.

You will lead a cross-functional team with product and test, align with roadmaps, and push standardization and automation to improve silicon first-pass success and time-to-market.

Qualifications

• Proven leader in digital IC design and verification at scale.
• Track record delivering mixed-signal SoCs end-to-end.
• Expertise in RTL design, FSM/control logic.
• Experience with verification methodologies (UVM, formal, AMS/DMS).

Responsibilities

• Own end-to-end digital design and verification delivery for the site.
• Establish and drive verification strategy (simulation, formal, AMS/DMS) as a coherent, evolving plan.
• Own digital architecture quality, including system control logic, FSM design, FW interfaces, and IP reuse.
• Define and enforce sign-off criteria, including coverage, closure metrics, and design quality gates.
• Align digital and verification execution with product roadmap, customer requirements, and business priorities.

Skills

Digital IC design

Verification leadership

RTL design

UVM/SystemVerilog

FSM/control logic

Cross-functional leadership

Tools

AMS/DMS co-simulation

Job description

Renesas Electronics seeks a senior leader to define and execute world-class digital design and verification at our Chandler site. You will own end-to-end delivery, establish verification strategy across simulation, formal, and AMS/DMS, and drive architecture quality from system control logic to IP reuse.

You will lead a cross-functional team with product and test, align with roadmaps, and push standardization and automation to improve silicon first-pass success and time-to-market.