Senior Digital Design Engineer - RTL, UVM, FPGA Prototyping

Silanna; San Diego (CA); On-site; USD 200,000 - 250,000; Full time

Benefits offered by this job

Discretionary annual bonus

Comprehensive benefits

Job summary

Silanna Semiconductors is seeking an experienced Senior Digital Design Engineer to contribute to the design and development of integrated circuit solutions related to Silanna’s mixed-signal technology.

The role encompasses RTL architecture, SystemVerilog/UVM verification, design integration, timing analysis, FPGA prototyping, and test bench debugging across the full IC development cycle. Strong communication and collaboration abilities are essential for success.

Qualifications

• Bachelor’s degree in electrical engineering (BSEE) required with relevant industry experience.
• Master’s (MSEE) preferred.
• 5+ years in digital IC/ASIC design and verification.
• Exposure to synthesis flows and physical design (e.g., place-and-route, timing closure, power optimization).
• Proficiency in UNIX/Linux and Python scripting is desirable.
• Experience with FPGA prototyping and emulation platforms is a plus.
• Background in mixed-signal design is advantageous.

Responsibilities

• Develop RTL designs in Verilog/SystemVerilog for complex digital and mixed-signal ICs.
• Define and implement verification environments using SystemVerilog and UVM methodologies.
• Create test plans, constrained-random testbenches, assertions, coverage models, and regression suites.
• Collaborate with system engineers to optimize circuit designs and system specification trade-offs.
• Perform block-level and top-level integration and verification.
• Analyze and debug functional, timing, CDC, reset, and integration issues.
• Support synthesis, static timing analysis, lint, CDC, and low-power verification flows.
• Assist with top-level assembly and design tapeout to semiconductor foundry.
• Collaborate with backend engineers on synthesis, floorplanning, timing closure, and PNR.

Skills

RTL design

SystemVerilog

UVM

Digital design fundamentals

Clock-domain crossing

Reset synchronization

Timing closure

ASIC/SoC development flows

Agent-based AI environments

Synthesis flows

Physical design

FPGA prototyping

Emulation platforms

UNIX/Linux

Python scripting

Education

Bachelor’s degree in Electrical Engineering (BSEE)

Master’s degree in Electrical Engineering (MSEE)

Tools

EDA tools

SystemVerilog/UVM environment

Job description

Silanna Semiconductors is seeking an experienced Senior Digital Design Engineer to contribute to the design and development of integrated circuit solutions related to Silanna’s mixed-signal technology.

The role encompasses RTL architecture, SystemVerilog/UVM verification, design integration, timing analysis, FPGA prototyping, and test bench debugging across the full IC development cycle. Strong communication and collaboration abilities are essential for success.