Senior Digital Design Engineer

Silanna Semi; San Diego (CA); On-site; USD 200,000 - 250,000; Full time

Benefits offered by this job

Comprehensive total rewards package

Discretionary annual bonuses

Support for work-life balance

Job summary

Silanna Semi in San Diego is looking for a Senior Digital Design Engineer to contribute to integrated circuit solution designs. This role requires expertise in RTL design, SystemVerilog/UVM methodologies, and collaboration for digital and mixed-signal systems.

The ideal candidate will have a background in electrical engineering, with 5+ years of relevant experience and a focus on innovative technology in a collaborative environment. The salary range is between $200,000 and $250,000 annually, complemented by a comprehensive benefits package.

Qualifications

• 5+ years in digital IC/ASIC design and verification.
• Familiarity with mixed-signal integration and modeling.
• Proficiency in UNIX/Linux and Python scripting.
• Strong technical communication skills.

Responsibilities

• Develop RTL designs for complex integrated circuits.
• Define and implement verification environments.
• Support synthesis and timing analysis.
• Collaborate with engineers on circuit designs.

Skills

RTL design

Verilog/SystemVerilog

UVM

digital IC architecture

DSP

functional verification

cross-functional collaboration

Education

Bachelor’s degree in electrical engineering

Master’s degree in electrical engineering

Tools

EDA tools

Python

UNIX/Linux

Job description

Silanna Semiconductors is actively seeking an experienced Senior Digital Design Engineer to contribute to the design and development of integrated circuit solutions related to Silanna’s innovative mixed-signal technology.

This position requires participation in all aspects of the IC development cycle including RTL architecture and design, SystemVerilog/UVM verification, design integration, synthesis support, timing analysis, FPGA prototyping, and test bench debug and characterization.

Experience with physical implementation flows including synthesis and place-and-route is highly desirable.

Essential Duties and Responsibilities

The team drives architecture, design, implementation, and verifcation of mixed-signal systems that include circuit blocks such as PLLs, DLLs, VCOs, ADCs, DACs, Filters, clock distribution and/or recovery systems.

• Develop RTL designs in Verilog/SystemVerilog for complex digital and mixed-signal integrated circuits
• Define and implement verification environments using SystemVerilog and UVM methodologies
• Create test plans, constrained-random testbenches, assertions, coverage models, and regression suites
• Collaborate with system engineers to optimize circuit designs and system specification trade-offs
• Perform block-level and top-level integration and verification
• Analyze and debug functional, timing, CDC, reset, and integration issues
• Support synthesis, static timing analysis, lint, CDC, and low‑power verification flows
• Assist with top‑level assembly and design tapeout to semiconductor foundry
• Collaborate with backend engineers on synthesis, floorplanning, timing closure, and place‑and‑route activities
• Create SystemVerilog models of the analog blocks
• Characterize and debug relevant blocks in silicon
• Perform bench testing and verification from prototype debug through production release
• Report the results of IC design, analysis, and evaluation

Required Skills and Experience

• Strong background in RTL design, digital IC architecture, DSP, and functional verification methodologies
• Solid understanding of Verilog/SystemVerilog, UVM, digital design fundamentals, clock-domain crossing, reset synchronization, timing closure, and ASIC/SoC
  development flows
• Familiarity with mixed-signal integration and modeling techniques
• Experience with industry-standard EDA tools for simulation, verification, synthesis, PNR, and debug
• Experience with bench testing, characterization, and debug of analog/mixed-signal circuits using test/measurement equipment and computer software
• Strong technical communication skills including verbal and writing skills
• Ability to work effectively in a collaborative, cross‑functional engineering environment

Experience

• Bachelor’s degree in electrical engineering (BSEE) required with relevant industry experience; Master’s (MSEE) preferred
• Preferably 5+ years in digital IC/ASIC design and verification
• Required familiarity with working in agent-based (Agentic) AI environments
• Exposure to synthesis flows and physical design (e.g., place‑and‑route, timing closure, power optimization) is a plus
• Proficiency in UNIX/Linux and strong Python scripting skills are desirable
• Experience with FPGA prototyping and emulation platforms is a plus
• Background in mixed-signal design is advantageous

Pay Range and Other Compensation and Benefits

USD $200,000 – $250,000 Annually

This role offers a competitive base salary – reflecting the full range for this location alongside a comprehensive total rewards package. In addition to base pay, compensation includes eligibility for discretionary annual bonuses, plus extensive benefits designed to support your work‑life balance.

EEO Employer: Silanna Semiconductor is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.