Senior Digital Clocking Architect & RTL Lead

Fortune 500

San Francisco (CA)

On-site

USD 180,000 - 240,000

Full time

2 days ago

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Job summary

Fortune 500 is seeking a Digital Mixed-Signal Lead to steer the architecture, RTL design, and clocking IP for advanced digital control infrastructures in mixed-signal subsystems. You will own the digital logic definitions driving PLLs, FLLs, and DLLs, collaborating closely with analog and verification teams.

The role demands 8+ years in digital ASIC design, deep SystemVerilog RTL expertise, and a track record of tapeouts across advanced nodes.

Qualifications

8+ years of professional digital ASIC design experience.
Deep expertise in writing robust, synthesizable SystemVerilog RTL.
Direct experience with advanced technology nodes, specifically N5, N3P, and beyond.
Proven history of steering cross-functional execution from initial concept through to successful tapeouts.

Responsibilities

Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.
Design complex digital control loops, state machines for adaptive calibration, DVFS controllers, and fractional-N delta-sigma modulators.
Serve as the primary bridge to Analog Circuit Designers and define clean boundaries at the analog-digital interface.
Partner with Verification Teams to drive MSV and RNM strategies for high-coverage loop simulations.
Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise.
Enforce a rigorous full-chip CDC and RDC sign-off methodology for the clocking network.