Senior DFT Verification Engineer - SystemVerilog & JTAG

Cisco Systems, Inc.; United States; On-site; USD 140,000 - 200,000; Full time

Job summary

Cisco Systems, Inc. in the Common Hardware Group (CHG) designs silicon, optics and hardware platforms powering Cisco's core switching, routing and wireless products worldwide.

The role focuses on DFT test planning, test benches for verification and collaboration with RTL and PD teams to validate test logic across the silicon lifecycle. The candidate will craft solutions, debug efficiently, and bring expertise in SystemVerilog, DFT verification and test bench development to ensure robust

Qualifications

• Bachelor's or Master's Degree in Electrical or Computer Engineering.
• 8+ years of experience in DFT verification and test planning.
• Experience in testbench development based on complex design specifications.
• Proficient in SystemVerilog for testbench development.
• Debugging experience with DVE/Verdi.
• Scripting skills: Tcl, Python or Perl.

Responsibilities

• You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive high-quality DFT verification.
• Develop detailed test plans and test benches to verify DFT architecture supporting ATE screening and in-system test.
• Collaborate with design, verification, and PD teams to integrate and validate test logic across all design phases.
• Contribute to innovative DFT and test strategy for new silicon models, bare die, and stacked die, enabling reusable test methods.
• Craft solutions and debug efficiently as part of the team.

Skills

DFT verification

Test bench development

Test planning

SystemVerilog

Debugging with DVE/Verdi

Scripting Tcl/Python/Perl

Education

Bachelor's or Master’s Degree in Electrical or Computer Engineering

Tools

DVE/Verdi

UVM

Job description

Cisco Systems, Inc. in the Common Hardware Group (CHG) designs silicon, optics and hardware platforms powering Cisco's core switching, routing and wireless products worldwide.

The role focuses on DFT test planning, test benches for verification and collaboration with RTL and PD teams to validate test logic across the silicon lifecycle. The candidate will craft solutions, debug efficiently, and bring expertise in SystemVerilog, DFT verification and test bench development to ensure robust