DFT Architect

Acceler8 Talent; San Francisco (CA); On-site; USD 275,000 - 300,000; Full time

Job summary

A leading technology firm is seeking an experienced DFT Architect in San Francisco to lead design-for-test strategies for advanced SoCs. Responsibilities include managing a team, DFT architecture, and collaborating for smooth integration. Ideal candidates have over 10 years of DFT experience with deep knowledge of relevant tools and a background in technical leadership.

Qualifications

• 10+ years of DFT experience, including 3+ years in technical leadership or management.
• Deep knowledge of DFT tools and flows.
• Strong understanding of RTL-to-GDSII flows and timing closure.

Responsibilities

• Define and own DFT architecture and methodology for advanced SoCs.
• Lead scan insertion, MBIST, LBIST, JTAG implementations.
• Manage and mentor a team of DFT engineers.

Skills

DFT experience

Technical leadership

Knowledge of DFT tools

RTL-to-GDSII flows

Scripting (Python, Perl, TCL)

Tools

Tessent

DFTMAX

Modus

Job description

Base pay range

$275,000.00/yr - $300,000.00/yr

In this role, you will work with Acceler8 Talent on a breakthrough computing initiative focused on real-time computing over encrypted datasets, enabling secure, high-performance processing in edge and cloud environments. Their proprietary architecture is designed for compute-heavy applications like Fully Homomorphic Encryption (FHE).

Overview

They’re looking for an experienced DFT Architect to lead the design-for-test strategy across complex SoC/ASIC programs. This is a hands-on leadership role for someone who can balance technical execution with team direction and cross-functional coordination.

In this role, you will

• Define and own DFT architecture and methodology for advanced SoCs
• Lead scan insertion, MBIST, LBIST, JTAG, boundary scan, and ATPG implementations
• Manage and mentor a team of DFT engineers through all phases of development
• Collaborate with RTL, PD, and verification teams for smooth DFT integration and signoff
• Support post-silicon bring-up, test development, and yield improvement efforts

You should bring

• 10+ years of DFT experience, including 3+ years in technical leadership or management
• Deep knowledge of DFT tools and flows (Tessent, DFTMAX, Modus, etc.)
• Hands-on experience with scan, BIST, and boundary scan techniques
• Strong understanding of RTL-to-GDSII flows, timing closure, and test coverage optimization
• Familiarity with scripting (Python, Perl, TCL) to automate and enhance test processes

Bonus if you have

• Background in safety-critical or mission-critical applications (automotive, aerospace, etc.)
• Experience with low-power DFT techniques and production ATE test optimization

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Industries
• Computer Hardware Manufacturing and Semiconductor Manufacturing