Senior DFT Engineer - RTL/ATPG & GPU IP Focus

Intel Corporation; Phoenix (AZ); Hybrid; USD 142,000 - 173,000; Full time

Job summary

Intel Corporation invites applications for a Senior DFT Design Engineer within the GPU Hardware IP (GHI) team of the Data Center Group. You will design, validate, and optimize RTL/GLS for Scan/ATPG aimed at graphics IPs and GPUs, while supporting post-silicon debugging and verification across the SoC.

You will collaborate with SoC customers to ensure high-quality GPU block integration, drive architecture and microarchitecture decisions, and contribute to Power, Performance, and Timing goals in a

Qualifications

• Bachelor's degree in Electrical or Computer Engineering with 4+ years of industry experience (or higher degrees with corresponding years).
• Experience with Scan/ATPG/DFT features and goals.
• Experience with SoC or IP DFT design, integration or verification.

Responsibilities

• Design, RTL/GLS validation, automation, and timing analysis for Scan/ATPG in graphics IPs.
• Develop RTL, perform verification, and support post-silicon debugging of ATPG content.
• Collaborate with SoC customers to ensure high-quality GPU block integration.

Skills

Scan

ATPG

SoC DFT design

IP DFT integration

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Siemens Tessent

ATPG tools

Synopsys VCS

Job description

Intel Corporation invites applications for a Senior DFT Design Engineer within the GPU Hardware IP (GHI) team of the Data Center Group. You will design, validate, and optimize RTL/GLS for Scan/ATPG aimed at graphics IPs and GPUs, while supporting post-silicon debugging and verification across the SoC.

You will collaborate with SoC customers to ensure high-quality GPU block integration, drive architecture and microarchitecture decisions, and contribute to Power, Performance, and Timing goals in a