Senior DFT Design Engineer - Graphics IP/GPU

Intel Corporation; Folsom (CA); Hybrid; USD 142,000 - 173,000; Full time

Job summary

Intel Corporation is seeking a Senior DFT Design Engineer in the US for the DCG GPU IP block. You will design RTL/GLS, validate ATPG, and contribute to trace/pattern generation and post-silicon support, ensuring high-quality integration into full chip designs.

The role requires a strong background in DFT features, SoC integration, and proficiency with Tessent or similar tools, within a hybrid work model at Intel locations across the US.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering or related STEM field with 4+ years of industry experience; or Master's with 3+ years; or PhD with 1+ year.
• Experience in Scan, ATPG or DFT features and SoC/IP DFT design, integration or verification.
• Proficiency with EDA tools such as Siemens Tessent or other ATPG tools, Synopsys VCS or equivalent.

Responsibilities

• Design RTL/GLS code and validate ATPG/DFT features for graphics IPs.
• Contribute to trace/pattern generation and post-silicon enablement and debug support.
• Review verification plans and drive unit-level verification across hierarchies.

Skills

Scan/ATPG

SoC DFT design

RTL development

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in Electrical/Computer Engineering

PhD in Electrical/Computer Engineering

Tools

Siemens Tessent

Synopsys VCS

Job description

Intel Corporation is seeking a Senior DFT Design Engineer in the US for the DCG GPU IP block. You will design RTL/GLS, validate ATPG, and contribute to trace/pattern generation and post-silicon support, ensuring high-quality integration into full chip designs.

The role requires a strong background in DFT features, SoC integration, and proficiency with Tessent or similar tools, within a hybrid work model at Intel locations across the US.