Senior DFT Engineer – Networking SoCs, On-Site

Arrow Components; Mountain View (CA); On-site; USD 101,000 - 123,000; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k with matching

Short-/Long-Term Disability Insurance

HSA/HRA options

Paid Time Off

Tuition Reimbursement

Growth opportunities

Job summary

eInfochips, an Arrow company, is seeking a Design for Test Engineer to drive DFT for advanced Networking SoCs. You will implement DFT flows, perform scan insertion, ATPG, and MBIST verification across multi‑nm designs, coordinating with RTL and silicon bring‑up teams.

The role requires 5–7 years of DFT experience, knowledge of Mentor Tessent and other EDA tools, and strong scripting (Perl/Shell/TCL). On-site in California with growth opportunities.

Qualifications

• 5–7 years of DFT experience in complex SoCs.
• Experience with scan insertion, ATPG, GLS and pattern simulations with/without timing.
• Experience in MBIST insertion and verification and JTAG insertion/verification.
• Proficient in scripting with Perl, Shell, TCL.

Responsibilities

• DFT implementation for 3nm and 5nm networking chips and IP DFT work.
• RTL checks for scan-insertion compatibility using Spyglass.
• Scan-Insertion using Tessent TestKompress and ATPG pattern generation.
• Pattern simulations with/without timing for multiple corners.
• MBIST insertion/verification on blocks and top, silicon bring-up.
• IEEE 1149.1 JTAG insertion and verification, scripting in Perl/Shell/TCL.
• DAeRT flow enhancement and Makefile scripting for automation.

Skills

DFT expert

Excellent communicator

Low power DFT

Networking SoCs

IEEE 1149.1 JTAG insertion

Education

B.Tech / M.Tech in Microelectronics/Electronics

Tools

Mentor Tessent

Cadence Modus

Synopsys Tetramax

Synopsys Spyglass

VCS

Verdi

Tessent TestKompress

Job description

eInfochips, an Arrow company, is seeking a Design for Test Engineer to drive DFT for advanced Networking SoCs. You will implement DFT flows, perform scan insertion, ATPG, and MBIST verification across multi‑nm designs, coordinating with RTL and silicon bring‑up teams.

The role requires 5–7 years of DFT experience, knowledge of Mentor Tessent and other EDA tools, and strong scripting (Perl/Shell/TCL). On-site in California with growth opportunities.