DFT Design Engineer I: SoC Validation & Debug

Cadence; Cary (NC); On-site; USD 89,000 - 165,000; Full time

Job summary

Cadence in Cary, NC seeks an experienced DFT engineer to define and implement SoC level DFT architectures spanning pre-silicon to post-silicon phases. You will develop, integrate and support SCAN, ATPG, MBIST, BSCAN and iJTAG, while driving DFT sign-off and collaborating with RTL, verification, physical design, and operations teams.

The role requires a BS degree and at least 3 years of hands-on SoC DFT experience, with scripting skills in TCL, Perl, or Python to automate flows.

Qualifications

• BS degree
• At least 3 years of hands‑on experience in SoC DFT.

Responsibilities

• Define and implement SoC level DFT architecture for large and complex designs.
• Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
• Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
• Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
• Support post-silicon debug, failure analysis and yield learning.
• Collaborate with RTL, verification, physical design and operation teams.

Skills

SCAN

ATPG

MBIST

Pre-silicon validation

Post-silicon debug

Cross-functional teamwork

Problem solving

Education

BS degree

Tools

TCL

Perl

Python

Job description

Cadence in Cary, NC seeks an experienced DFT engineer to define and implement SoC level DFT architectures spanning pre-silicon to post-silicon phases. You will develop, integrate and support SCAN, ATPG, MBIST, BSCAN and iJTAG, while driving DFT sign-off and collaborating with RTL, verification, physical design, and operations teams.

The role requires a BS degree and at least 3 years of hands-on SoC DFT experience, with scripting skills in TCL, Perl, or Python to automate flows.