Design For Test Engineer (Einfochips Inc)

Arrow Electronics; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401(k) with matching contributions

Short‑Term/Long‑Term Disability Insurance

Health Savings Account options

Paid Time Off

Tuition Reimbursement

Growth opportunities

Job summary

Arrow Electronics is looking for a Design For Test Engineer based in San Jose, CA. The role includes DFT implementation, scan-insertion, and ATPG pattern generation for networking chips. Candidates should have 5–7 years of relevant experience and a degree in Microelectronics/Electronics. The position offers comprehensive benefits including medical insurance and a 401(k) plan. This is a fully on-site position requiring potential travel to client locations.

Qualifications

• 5–7 years of experience in DFT.
• Expertise in scan-insertion, ATPG, and pattern simulations.
• Experience with MBIST insertion and JTAG verification.

Responsibilities

• Implement DFT for 3nm and 5nm networking chips.
• Conduct RTL checks for scan-insertion compatibility.
• Generate ATPG patterns and perform silicon debug.

Skills

DFT implementation

Scan-insertion expertise

ATPG pattern generation

Pattern simulation

Scripting with Perl

Experience with MBIST

IEEE 1149.1 JTAG verification

Communication skills

Low-power DFT expertise

Education

B.Tech or M.Tech in Microelectronics/Electronics

Tools

Synopsys Spyglass

Mentor Tessent

VCS

Job description

Position

Design For Test Engineer (Einfochips Inc)

What You'll Be Doing

• DFT implementation for 3nm and 5nm networking chips, IP DFT work
• RTL checks for scan-insertion compatibility using Synopsys Spyglass
• Scan-insertion using Tessent TestKompress
• ATPG pattern generation (compressed and uncompressed mode)
• Pattern simulation without timing and with timing for different corners (using VCS)
• Mismatch debug using Verdi
• Scripting with Perl, Shell, TCL for DFT flow enhancement/automation in project
• Makefile enhancement using extended scripts and targets for flow enhancement
• MBIST insertion and verification on block level and top level
• Silicon debug and bring-up for block and top
• IEEE 1149.1 JTAG insertion and verification

What We’re Looking For

• 5–7 years of experience in DFT
• Expertise in scan-insertion, ATPG, GLS, pattern simulations (with and without timing)
• Experience with MBIST insertion and verification
• Experience in IEEE 1149.1 JTAG insertion and verification
• Proficiency in scripting languages like Perl, Shell, TCL
• Worked on multi‑million gate count SoCs in networking, consumer, and various IPs such as PLL, Serdes
• Experience with Mentor Tessent
• B.Tech or M.Tech in Microelectronics/Electronics
• Excellent communication skills
• Low‑power DFT expertise

Benefits

• Medical, Dental, Vision Insurance
• 401(k) with matching contributions
• Short‑Term/Long‑Term Disability Insurance
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) options
• Paid Time Off
• Tuition Reimbursement
• Growth opportunities

Work Arrangement: Fully on‑site – must be able to travel to an Arrow client office location as requested.

Location

San Jose, CA

EEO Statement

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)