Senior DFT Engineer: MBIST, ATPG & Silicon Bring-up

Eastridge Workforce Solutions; San Diego (CA); Vor Ort; USD 208.000 - 270.000; Vollzeit

Zusammenfassung

Eastridge Workforce Solutions is seeking an experienced Design-for-Test (DFT) Engineer in San Diego, CA. The role focuses on implementing DFT methodologies for RF, Bluetooth, and WLAN chipsets, working closely with Front-End and Physical Design teams.

A minimum of 5+ years DFT experience, MBIST and Tessent flow expertise, and scripting skills are required. The position is a contract, full-time role with expected hands-on support for memory BIST, ATPG, and scan compression, plus VTRAN pattern

Qualifikationen

• 5+ years of hands-on DFT experience.
• MBIST experience with Siemens Tessent Flow.
• Experience with ATPG and Tetramax.
• Experience with scan compression (SEQ/Ultra/TestKompress).
• Gate-level simulation and debugging experience.
• Verilog/SystemVerilog RTL experience.
• Scripting/automation with Tcl, Perl, Python.

Aufgaben

• Implement DFT methodologies for advanced semiconductor designs.
• Develop MBIST using Siemens Tessent Flow.
• Perform gate-level simulations and debug failures.
• Implement scan compression using SEQ, Ultra, or TestKompress.
• Develop ATPG using Tetramax.
• Support ATPG diagnosis and ATE debug.
• Translate DFT patterns using VTRAN.
• Create automation/scripts with Tcl/Perl/Python.
• Work with RTL in Verilog/SystemVerilog.
• Assist timing/constraints with PrimeTime.
• Collaborate with Front-End, Physical Design and Test teams.
• Troubleshoot complex DFT and silicon test issues.

Kenntnisse

DFT experience

Memory BIST

ATPG

Gate-level simulation

Verilog/SystemVerilog RTL

Scripting (Tcl/Perl/Python)

Scan compression (SEQ/Ultra/TestKomP)

VTRAN pattern translation

Tools

Siemens Tessent Flow

Tetramax

PrimeTime

VTRAN

Jobbeschreibung

Eastridge Workforce Solutions is seeking an experienced Design-for-Test (DFT) Engineer in San Diego, CA. The role focuses on implementing DFT methodologies for RF, Bluetooth, and WLAN chipsets, working closely with Front-End and Physical Design teams.

A minimum of 5+ years DFT experience, MBIST and Tessent flow expertise, and scripting skills are required. The position is a contract, full-time role with expected hands-on support for memory BIST, ATPG, and scan compression, plus VTRAN pattern