Senior DFT Engineer for SoCs (3nm/5nm)

Arrow Electronics, Inc.; San Jose (CA); On-site; USD 96,000 - 171,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

Job summary

Arrow Electronics, Inc. through its eInfochips unit in San Jose, CA is seeking a Design For Test Engineer III for advanced DFT work on 3nm/5nm networking chips and various IPs. You will handle scan insertion, ATPG, pattern simulations, and silicon bring‑up across multi‑million gate count SoCs, using Mentor Tessent, VCS, Verdi, and related tools.

The role requires strong scripting in Perl/Shell/TCL, and collaboration with QA and design teams to enhance DFT flows and automation.

Qualifications

• 5–7 years of experience in DFT required.
• Experience in IEEE 1149.1 JTAG Insertion and verification.
• Experience with multi‑million gate count SoCs in Networking/Consumer IPs.

Responsibilities

• DFT implementation for 3nm and 5nm Networking chips and IP DFT work.
• RTL checks for scan‑insertion compatibility using Synopsys Spyglass.
• Scan‑Insertion using Tessent TestKompress and MBIST insertion/verification.

Skills

Perl

Shell

TCL

Excellent communicator

Education

B.Tech / M.Tech in Microelectronics / Electronics

Tools

Mentor Tessent

Cadence Modus

Synopsys Tetramax

VCS

Verdi

Job description

Arrow Electronics, Inc. through its eInfochips unit in San Jose, CA is seeking a Design For Test Engineer III for advanced DFT work on 3nm/5nm networking chips and various IPs. You will handle scan insertion, ATPG, pattern simulations, and silicon bring‑up across multi‑million gate count SoCs, using Mentor Tessent, VCS, Verdi, and related tools.

The role requires strong scripting in Perl/Shell/TCL, and collaboration with QA and design teams to enhance DFT flows and automation.