DFT Engineer for LEO ASICs & RFIC

Amazon; San Diego (CA); On-site; USD 136,000 - 184,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC in San Diego is seeking a DFT Engineer to help define and implement digital chip SOCs for LEO satellite communications and Amazon gateways.

You will collaborate with ASIC and RFIC teams to integrate DFT logic (MBIST, clock controls, JTAG), optimize fault coverage, and advance automated DFT insertion and validation using AI-enhanced workflows. The role requires a Bachelor’s in EE and 2+ years of DFT experience.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 2+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation.

Responsibilities

• Architect and define DFT solutions adapted to the specific use of various LEO’s chips.
• Contribute to the improvement and customization of IPs and DFT methodology while embracing AI flow.
• Work with the ASIC design teams in all the sites to incorporate DFT logic like MBIST, clock controls and JTAG controllers.
• Work with RFIC teams to ensure maximum fault coverage on the custom RF blocks.
• Ensure that blocks meet DFT, timing and power targets by working closely with the implementation team.
• Work closely with the Test engineering team to help translate the ATE patterns to tester format.
• Work with the test team to do jointly bring up the digital portions of the LEO chips.

Skills

DFT techniques

Automation scripts

Logic BIST

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical or Communications Engineering

Tools

Logic BIST

Job description

Amazon Kuiper Manufacturing Enterprises LLC in San Diego is seeking a DFT Engineer to help define and implement digital chip SOCs for LEO satellite communications and Amazon gateways.

You will collaborate with ASIC and RFIC teams to integrate DFT logic (MBIST, clock controls, JTAG), optimize fault coverage, and advance automated DFT insertion and validation using AI-enhanced workflows. The role requires a Bachelor’s in EE and 2+ years of DFT experience.