Senior DFT & RTL Design Engineer – GPU IP

Intel Corporation; Phoenix (AZ); Hybrid; USD 142,000 - 173,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation in the United States (Arizona/Phoenix) seeks a Senior DFT Design Engineer to advance RTL/GLS validation, ATPG, and test pattern development for graphics IP and GPU integration.

You will define architecture features, optimize logic for power, performance, and area, review verification plans, and collaborate with SoC teams to ensure high-quality silicon from design through post-silicon support. The role is hybrid with on-site and remote work options.

Qualifications

• Bachelors/Masters/PhD in Electrical Engineering, Computer Engineering or related STEM + industry experience as described.
• Experience with Scan, ATPG or other DFT features.
• Experience with SoC or IP DFT design, integration or verification.

Responsibilities

• Design RTL/GLS coding and simulation for graphics IPs and GPU blocks.
• Verify features across verification hierarchies and address failing RTL tests.
• Support SoC customers to ensure high-quality integration and debugging.

Skills

DFT features

ATPG/DFT design

RTL/GLS validation

EDA tools (Tessent,VCS)

Education

Bachelor's in Electrical/Computer Eng or related STEM

Master's in Electrical/Computer Eng or related STEM

PhD in Electrical/Computer Eng or related STEM

Tools

Siemens Tessent

Synopsys VCS

Job description

Intel Corporation in the United States (Arizona/Phoenix) seeks a Senior DFT Design Engineer to advance RTL/GLS validation, ATPG, and test pattern development for graphics IP and GPU integration.

You will define architecture features, optimize logic for power, performance, and area, review verification plans, and collaborate with SoC teams to ensure high-quality silicon from design through post-silicon support. The role is hybrid with on-site and remote work options.