Senior Design Verification Lead (Hybrid) – SoC & Power

Powerlattice Technologies Inc; Chandler (AZ); Hybrid; USD 160,000 - 190,000; Full time

Benefits offered by this job

Stock options

Health, dental, vision, and 401(k)

Job summary

Powerlattice Technologies Inc. seeks an experienced Design Verification Lead to drive verification for complex SoC/IP designs. You will build scalable SystemVerilog-based environments, define verification strategies, and establish reusable test infrastructure.

You will collaborate with RTL, analog, architecture, and silicon validation teams to ensure thorough coverage and timely signoff, while mentoring a growing verification group.

Qualifications

• 10+ years of experience in digital verification of SoCs with ownership of subsystems or full-chip verification.
• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
• Hybrid role requiring 3 days onsite at HQ in Vancouver, WA or Chandler, AZ.
• Experience with industry-standard EDA tools (Synopsys, Cadence) and modern verification approaches.

Responsibilities

• Lead verification planning and execution for complex digital and mixed-signal subsystems.
• Architect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure.
• Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements.
• Develop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces.
• Perform RTL and gate-level simulation, including GLS with SDF annotations to identify issues.
• Develop and optimize regression and GLS flows using Xcelium and VCS.
• Provide technical leadership to a team of verification engineers and mentor them.

Skills

Verilog

SystemVerilog

UVM

Python

Education

Electrical/Computer Engineering degree

Tools

Xcelium

VCS

Job description

Powerlattice Technologies Inc. seeks an experienced Design Verification Lead to drive verification for complex SoC/IP designs. You will build scalable SystemVerilog-based environments, define verification strategies, and establish reusable test infrastructure.

You will collaborate with RTL, analog, architecture, and silicon validation teams to ensure thorough coverage and timely signoff, while mentoring a growing verification group.