Senior Design Verification Lead, SoC Power Chips (Hybrid)

Powerlattice Technologies Inc; Vancouver (WA); Hybrid; USD 160,000 - 190,000; Full time

Benefits offered by this job

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Benefits package

Job summary

Powerlattice Technologies Inc seeks a Design Verification Lead to spearhead verification of complex SoCs/IPs, building scalable SystemVerilog environments and reusable test infrastructure. The role collaborates with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues.

The candidate will drive coverage closure, develop assertions and functional checkers, and lead a team of verification engineers in a hybrid setup across Vancouver, WA and Chandler, AZ.

Qualifications

• 10+ years of digital verification experience in SoCs
• Ownership of subsystems or full-chip verification
• Experience with SystemVerilog-based verification environments

Responsibilities

• Lead verification planning and execution for complex digital and mixed-signal subsystems
• Architect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure
• Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements
• Develop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces
• Perform and support CDC verification for async and sync clock-domain interfaces
• Develop and maintain UVM-based infrastructure and RAL models where applicable
• Develop checkers, scoreboards, reference models, assertions, and functional coverage
• RTL and gate-level simulation including GLS/SDF annotations
• Regression and GLS flows using Xcelium and VCS
• Analyze coverage and drive closure by identifying verification gaps
• Debug RTL/testbench/simulation/gate-level failures via waveform/logs
• Collaborate with RTL/analog teams to reproduce root causes and drive fixes
• Review specs/RTL for corner cases and interface issues
• Translate silicon validation findings into test scenarios
• Provide technical leadership and mentorship to verification engineers

Skills

Verilog

SystemVerilog

UVM

SVA

Constrained-random

Coverage-driven verification

Python scripting

Debugging

RTL/gate-level simulation

Mentoring

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Xcelium

VCS

Job description

Powerlattice Technologies Inc seeks a Design Verification Lead to spearhead verification of complex SoCs/IPs, building scalable SystemVerilog environments and reusable test infrastructure. The role collaborates with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues.

The candidate will drive coverage closure, develop assertions and functional checkers, and lead a team of verification engineers in a hybrid setup across Vancouver, WA and Chandler, AZ.