Senior SoC Verification Lead

Anysilicon; Austin (TX); Hybrid; USD 150,000 - 220,000; Full time

Job summary

Efficient seeks a Design Verification Lead to steer functional verification of complex SoC/IP designs within its hardware eng org, ensuring high-quality verification ahead of market release.

The role emphasizes end-to-end strategy, scalable UVM environments, and a proactive approach to coverage, debugging, and sign-off across multi-block interactions. Collaboration with RTL, physical design, and post-silicon teams is essential.

Qualifications

• 10+ years in ASIC/SoC design verification with increasing responsibilities.
• At least 3 years in a lead role owning verification strategy, sign-off, and team execution.
• Strong academic background complemented by practical industry experience.

Responsibilities

• Define end-to-end verification strategy across block, subsystem, and full-chip levels.
• Architect scalable UVM-based testbenches with agents, scoreboards, and coverage monitors.
• Develop constrained-random stimulus and coverage-driven verification plans.
• Apply SystemVerilog Assertions for protocol compliance and invariants.
• Coordinate boot sequences, power-on resets, and multi-block interactions at tapeout readiness.
• Lead bug lifecycle, triage, tracking, fix verification, and cross-functional resolution.

Skills

UVM-based testbench

SystemVerilog verification

Functional coverage

Debug complex simulations

SoC building blocks knowledge

Education

Bachelor's or Master's/PhD in EE or CE

Job description

Efficient seeks a Design Verification Lead to steer functional verification of complex SoC/IP designs within its hardware eng org, ensuring high-quality verification ahead of market release.

The role emphasizes end-to-end strategy, scalable UVM environments, and a proactive approach to coverage, debugging, and sign-off across multi-block interactions. Collaboration with RTL, physical design, and post-silicon teams is essential.