AI Accelerator Verification Architect

Acceler8 Talent; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Visa sponsorship available

Job summary

Acceler8 Talent is seeking a Senior Design Verification Engineer to own a verification domain within a cutting-edge AI accelerator program. You will lead strategy, execution and functional closure for IP, subsystems, and full-chip verification, partnering with hardware and software teams to deliver robust pre-silicon validation.

You will build end-to-end verification strategies, develop scalable UVM testbenches, and drive emulation flows.

Qualifications

• Minimum five years of pre-silicon verification with ownership of IP/subsystems.
• Strong experience in block/subsystem verification, CPU subsystem/IP integration, full-chip verification, emulation, DMA/NoC, or multi-SoC/die-to-die protocols.
• Expertise in UVM methodology and testbench architecture; capable of debugging complex designs.
• Ability to interpret specifications from hardware and software perspectives.

Responsibilities

• Own a verification domain, from specs to debug and functional closure.
• Develop end-to-end verification strategies spanning IP, SoC-level testing, and emulation.
• Build and maintain UVM testbench architecture for complex accelerator designs.
• Collaborate with hardware and software teams to identify verification gaps and resolve failures.
• Develop and apply AI-assisted verification and emulation flows to accelerate development.

Skills

Pre-silicon verification ownership

UVM methodology

Testbench architecture

SoC/IP integration verification

Debugging complex designs

Spec interpretation (HW/SW)

Tools

Palladium

Veloce

RISC-V verification tools

Job description

Acceler8 Talent is seeking a Senior Design Verification Engineer to own a verification domain within a cutting-edge AI accelerator program. You will lead strategy, execution and functional closure for IP, subsystems, and full-chip verification, partnering with hardware and software teams to deliver robust pre-silicon validation.

You will build end-to-end verification strategies, develop scalable UVM testbenches, and drive emulation flows.