Design Verification Engineer for AI Accelerator SoC

Acceler8 Talent; San Francisco (CA); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Equity participation

Medical, dental, vision coverage

401(k)

Paid time off

Job summary

Acceler8 Talent seeks an experienced Design Verification Engineer to verify IP, subsystems, and full-chip functionality for an AI accelerator. You will collaborate with architecture, RTL, and software teams to ensure first-pass silicon success and scalable verification methodologies.

Responsibilities include owning verification of major areas, building AI-assisted workflows, and developing reusable UVM environments.

Qualifications

• 5+ years of hands-on pre-silicon verification in ASIC/SoC environments.
• Strong experience in block or subsystem verification and full-chip verification.
• Deep understanding of UVM, constrained-random verification, and scalable testbench architecture.
• Ability to translate hardware/software specs into effective verification strategies.
• Interest in AI-assisted development workflows and automation.

Responsibilities

• Own verification for a major functional area based on your expertise.
• Define and execute verification strategies across IP, subsystem, SoC, and emulation environments.
• Build AI-assisted verification workflows to improve productivity and cycle times.
• Develop reusable UVM-based environments, test plans, stimulus, and coverage models.
• Debug complex design issues and drive functional closure with design/architecture teams.
• Contribute to verification methodology improvements for future silicon programs.

Skills

UVM

Constrained-random verification

Testbench architecture

AI-assisted verification

Emulation

Tools

Cadence Palladium

Siemens Veloce

Job description

Acceler8 Talent seeks an experienced Design Verification Engineer to verify IP, subsystems, and full-chip functionality for an AI accelerator. You will collaborate with architecture, RTL, and software teams to ensure first-pass silicon success and scalable verification methodologies.

Responsibilities include owning verification of major areas, building AI-assisted workflows, and developing reusable UVM environments.