Senior Digital Verification Engineer

AndGate Informatics Pvt. Ltd.; California (MO); On-site; USD 120,000 - 160,000; Full time

Job summary

AndGate Informatics Pvt. Ltd. is seeking an experienced Digital Verification Engineer to own the functional verification of complex SoC/ASIC designs from testbench architecture through coverage closure and sign-off.

You will architect UVM/SystemVerilog testbenches, develop verification plans, drive coverage closure, write SVA assertions, debug failures, and collaborate with design and DFT teams to advance methodology and regression infrastructure.

Qualifications

• 5+ years of hands-on digital/functional verification experience.
• Strong SystemVerilog and UVM; solid grasp of SVA, constrained-random, and coverage-driven verification.
• Experience with industry simulators (Xcelium / VCS / Questa) and debug flows.
• Proven track record across at least one tape-out.
• Clear communicator who can work independently and own deliverables.

Responsibilities

• Architect and build UVM/SystemVerilog testbenches for block- and SoC-level verification
• Develop verification plans, drive coverage closure (functional + code), and own sign-off quality
• Write SVA assertions and constraints, debug complex failures, and collaborate with design and DFT teams
• Contribute to methodology, reuse, and regression infrastructure.

Skills

SystemVerilog

UVM

SVA

Constrained-random

Coverage-driven verification

Tape-out experience

Tools

Xcelium

VCS

Questa

Job description

We are hiring experienced Digital Verification Engineers to own the functional verification of complex SoC/ASIC designs from testbench architecture through coverage closure and sign-off.

What you'll do

• Architect and build UVM/SystemVerilog testbenches for block- and SoC-level verification
• Develop verification plans, drive coverage closure (functional + code), and own sign-off quality
• Write SVA assertions and constraints, debug complex failures, and collaborate with design and DFT teams
• Contribute to methodology, reuse, and regression infrastructure.

What we're looking for

• 5+ years of hands-on digital/functional verification experience (block and/or SoC level)
• Strong SystemVerilog and UVM; solid grasp of SVA, constrained-random, and coverage-driven verification
• Experience with industry simulators (Xcelium / VCS / Questa) and debug flows
• Proven track record across at least one tape-out
• Clear communicator who can work independently and own deliverables

Location & eligibility

• US-based candidates only. You must currently reside in the United States and be authorized to work in the US without sponsorship.