Senior Design Verification Engineer

BayOne Solutions; San Jose (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

A leading company is looking for a Senior Staff System IP Design Verification Engineer to lead verification efforts for advanced System IP. This hands-on role requires expertise in UVM, SystemVerilog, and gate-level simulation. You'll develop testbenches, drive automation, and collaborate with design teams, ensuring thorough verification processes. Ideal candidates will have extensive experience in DV and strong debugging skills.

Qualifications

• 12+ years of DV experience required.
• 5+ years of hands-on skills in UVM, SystemVerilog, and GLS.

Responsibilities

• Develop reusable testbenches and verification environments.
• Create and execute test plans, debug regressions, and close coverage.
• Perform GLS and power-aware verification.

Skills

UVM

SystemVerilog

Debugging

Collaboration

Communication

Education

BS/MS/PhD in EE/CE

Tools

Gate-level simulation

Scripting

Job description

Job Overview

We're seeking a Senior Staff System IP Design Verification Engineer to lead verification efforts for advanced System IP, including coherent interconnects and caches. This hands-on role requires extensive experience in UVM, SystemVerilog, and gate-level simulation (GLS).

Key Responsibilities

• Develop reusable testbenches and verification environments from scratch
• Drive best practices and automation
• Create and execute test plans, debug regressions, and close coverage
• Perform GLS, power-aware (UPF) verification, and post-silicon support
• Collaborate with design, SoC, and physical teams

Requirements

• BS/MS/PhD in EE/CE with 12+ years of DV experience
• Strong hands-on skills in UVM, SystemVerilog, GLS (5+ years), and scripting
• Familiarity with ARM protocols (CHI, AXI, etc.)
• Experience in IP bring-up, silicon debug, and low-power verification
• Excellent debugging, collaboration, and communication skills