Silicon Verification Engineer

Randstad USA; Mountain View (CA); Remote; USD 150,000 - 200,000; Full time

Job summary

A Silicon Verification Engineer is sought for a leading technology company, focusing on UVM-based verification for high-speed SoC interfaces. This role involves collaboration across design teams and offers remote work options. Ideal candidates will have strong SystemVerilog and UVM knowledge, with a Bachelor's degree in a relevant field.

Benefits

Comprehensive benefits package

Health insurance

401K contribution

Qualifications

• 2+ years of experience preferred, ideally 3-6 years.

Responsibilities

• Develop and execute UVM-based verification plans for SoC interfaces.
• Define, document, and implement UVM verification environments.
• Run RTL and Gate Level Netlist simulations, debug failures.

Skills

SystemVerilog

UVM

Automation

Coding

Education

Bachelor's degree in EE, CE, CS, or related field

Job description

job summary:
A Silicon Verification Engineer is needed for an American multinational technology company that develops, manufactures, licenses, supports, and sells computer software, consumer electronics, personal computers, and related services. Remote (prefer PST hours) work. The Silicon Verification Engineer is responsible for developing and executing UVM-based verification plans for high-speed SoC interfaces used in AI and compute chips, with a focus on SystemVerilog, mixed signal verification, and collaboration across design teams.


location: Remote, Remote
job type: Contract
salary: $36.66 - 71.69 per hour
work hours: 8am to 5pm
education: Bachelors

responsibilities:

• Team focuses on IP verification of high-speed interfaces connecting components within an SoC.
  
  
• Role contributes to internal AI and compute projects, including Certus and CRDAS high-speed serial interfaces.
  
  
• Offers the chance to work on advanced AI chips, an exciting and rapidly growing field.
  
  
• Define, document, and implement UVM verification environments.
  
  
• Write and implement test plans using SystemVerilog/UVM (tests, benches, coverage, checkers).
  
  
• Run RTL and Gate Level Netlist simulations, debug failures, and propose fixes.
  
  
• Support post-silicon verification activities with design and product teams.

Skills:

• strong SystemVerilog and UVM knowledge required.
  
  
• Mixed signal verification (analog/digital) experience preferred.
  
  
• Fluent in design verification methodologies (UVM/VMM/OVM).

Education and Experience:

• Bachelor's degree in EE, CE, CS, or related field required.
  
  
• 2+ years of experience (ideal: 3-6 years).

#LI-AG1


qualifications:

• Experience level: Experienced
• Education: Bachelors

skills:

Automation

Coding

Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

At Randstad, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact [e-mail].

Pay offered to a successful candidate will be based on several factors including the candidate's education, work experience, work location, specific job duties, certifications, etc. In addition, Randstad offers a comprehensive benefits package, including health, an incentive and recognition program, and 401K contribution (all benefits are based on eligibility).

This posting is open for thirty (30) days.

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance.

Qualified applicants in the unincorporated areas of Los Angeles County with criminal histories will be considered for employment in accordance with the Los Angeles County's Fair Chance Ordinance for Employers.

We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles' Fair Chance Initiative for Hiring Ordinance.