Senior ASIC Design Verification Engineer, TPU Compute

Google; Sunnyvale (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

A leading company is seeking a Senior ASIC Design Verification Engineer to shape the future of AI/ML hardware acceleration. The role involves verifying complex digital designs and collaborating with design engineers to develop custom silicon solutions for TPU technology.

Qualifications

• 7 years of experience with industry standard tools relevant to silicon-based ICs.
• Experience in verifying digital logic at RTL using SystemVerilog for ASICs.

Responsibilities

• Plan the verification of complex digital design blocks.
• Create a constrained-random verification environment using SystemVerilog and UVM.
• Debug tests with design engineers to ensure functional correctness.

Skills

SystemVerilog

Digital Logic Verification

Power-aware Verification

Education

Bachelor's degree in Electrical Engineering

Master's degree or PhD in Electrical Engineering

Job description

Join to apply for the Senior ASIC Design Verification Engineer, TPU Compute role at Google.

**Minimum qualifications:**

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 7 years of experience with industry standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.
• Experience with SystemVerilog (e.g., SystemVerilog Assertions or functional coverage).

**Preferred qualifications:**

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• 10 years of experience with industry standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.
• Experience in verifying digital logic at RTL using SystemVerilog for ASICs.
• Experience in memory subsystem design verification.
• Experience in Power-aware verification, Gate-level simulations, and Post-silicon bring-up.
• Familiarity with ASIC standard interfaces and memory system architecture.

**About The Job:**

In this role, you’ll work to shape the future of AI/ML hardware acceleration, specifically focusing on TPU architecture and its integration within AI/ML-driven systems. You will verify complex digital designs, collaborate with design engineers, and contribute to the development of custom silicon solutions that power Google’s TPU technology.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud, emphasizing security, efficiency, and reliability.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Salary ranges depend on location, skills, experience, and education. Your recruiter can provide specific details during the hiring process.

**Responsibilities:**

1. Plan the verification of complex digital design blocks by understanding design specifications and collaborating with design engineers.
2. Create a constrained-random verification environment using SystemVerilog and UVM.
3. Develop coverage measures for stimulus and corner-case scenarios.
4. Debug tests with design engineers to ensure functional correctness.
5. Close coverage measures, identify verification gaps, and demonstrate progress towards tape-out.

Google is an equal opportunity employer and committed to diversity and inclusion. We consider all qualified applicants regardless of race, color, religion, sex, national origin, sexual orientation, age, disability, or veteran status. If you require accommodations, please contact us through the provided form.