Senior Design Verification Engineer

Ventana Micro Systems; Cupertino (CA); On-site; USD 115,000 - 268,000; Full time

Job summary

Join a forward-thinking semiconductor startup at the forefront of RISC-V and Chiplet Architecture. As a Design Verification Engineer, you'll play a crucial role in advancing innovative processors and subsystems. This dynamic position involves developing verification plans, constructing testbenches, and debugging designs throughout the project lifecycle. With a strong emphasis on collaboration and independence, you'll contribute to cutting-edge technology solutions for cloud, enterprise, and edge computing. If you're passionate about computer architecture and eager to make an impact in a rapidly evolving industry, this opportunity is perfect for you.

Qualifications

• 4+ years of experience in design verification.
• Strong knowledge of CPU microarchitectures.
• Ability to work independently and collaboratively.

Responsibilities

• Develop and execute verification plans for units and features.
• Build testbenches and stimulus generators.
• Debug designs across simulation and silicon stages.

Skills

SystemVerilog verification development

C/C++ programming

Python programming

Computer architecture knowledge

UVM or similar methodologies

Education

Bachelor’s degree in engineering

Master’s degree in engineering

Tools

Testbenches

Stimulus generators

Scoreboards

Job description

Ventana Micro Systems is at the forefront of the two hottest trends revolutionizing the semiconductor industry: RISC-V and Chiplet Architecture. Check out our CEO discussing with global tech analyst Patrick Moorhead how Ventana combines RISC-V's extensibility with chiplet technology to drive customer innovation for data center solutions.

The company is well-funded, backed by major strategic investors, with a mission to develop top-tier CPU cores for cloud, enterprise, 5G, and Edge computing. Join us and be part of one of the most exciting semiconductor startups in the industry.

We are hiring multiple Design Verification engineers to advance our innovative RISC-V processors and subsystems.

Role:

1. Develop and execute verification plans for units and features.
2. Build testbenches, scoreboards, and stimulus generators.
3. Implement functional coverage models.
4. Debug designs across simulation, prototyping, and silicon stages.

Qualifications Required:

• 4+ or 8+ years of industry experience.
• Bachelor’s or Master’s degree in a related engineering field.
• Ability to work independently and collaboratively across geographies.
• Strong knowledge of computer architecture.

Preferred Skills and Qualifications:

• SystemVerilog verification development experience.
• Experience with UVM or similar methodologies for testbench construction.
• Experience with scoreboards and stimulus generators for complex units.
• Industry experience with CPU microarchitectures (x86, ARM, RISC-V, etc.) or coherent caching systems.
• Software development skills in C/C++ and Python.
• Ownership of units or features throughout the project lifecycle.

Salary Range:

$115,000 to $268,000 per year.

EEOE Statement:

Ventana is an Equal Employment Opportunity Employer. We value diversity and an inclusive environment where all individuals are respected and valued. We consider all qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, age, disability, gender identity, marital status, veteran status, or any other protected category.

COVID-19 Policy:

We encourage vaccination, including boosters when eligible. Proof of vaccination or a negative PCR test is required to work on-site or meet with clients.

Notice to Recruiters:

External recruiters and staffing agencies must have a valid contract with Ventana. Unsolicited resumes are considered submissions without obligation. We reserve the right to contact candidates directly and will not be liable for fees unless a formal agreement is in place.

Note: Please ensure you apply through our official careers page to avoid job scams.