Senior Design Verification Architect for DDR & Memory

Renesas Electronics Corporation; Chandler (AZ); On-site; USD 140,000 - 200,000; Full time

Job summary

Renesas Electronics Corporation is seeking a Principal Design Verification Engineer in Chandler, AZ to provide technical leadership for verification of next‑generation semiconductor memory interface products, including data buffer silicon.

You will drive verification strategy and execution for complex digital designs, employing SystemVerilog and UVM, with opportunities to lead and mentor a verification team across block and system level verification.

Qualifications

• Extensive semiconductor design verification experience with ownership of complex verification efforts.
• Expert-level proficiency with SystemVerilog and UVM.
• Experience defining verification strategies and verification plans from design specs.
• Strong skills in functional verification, constrained-random testing, and coverage closure.
• Proven ability to lead and mentor a verification team.

Responsibilities

• Lead verification strategy and execution for complex designs at block and system level.
• Define verification methodologies, test plans, coverage strategies and environments.
• Architect, develop and optimize SystemVerilog/UVM testbenches and environments.
• Drive test development, coverage, checkers, CR testing, and coverage closure.
• Provide technical guidance and mentorship to verification engineers.
• Collaborate with RTL/design teams to meet functional and performance requirements.

Skills

SystemVerilog

UVM

Technical leadership

Mentoring

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field

Tools

SystemVerilog/UVM testbenches

Job description

Renesas Electronics Corporation is seeking a Principal Design Verification Engineer in Chandler, AZ to provide technical leadership for verification of next‑generation semiconductor memory interface products, including data buffer silicon.

You will drive verification strategy and execution for complex digital designs, employing SystemVerilog and UVM, with opportunities to lead and mentor a verification team across block and system level verification.