Senior Design Engineer: High-Speed L2 Cache for AI

Tachyum; Sunnyvale (CA); On-site; USD 150,000 - 300,000; Full time

Benefits offered by this job

Competitive salary

Professional development

International environment

Bleeding edge technology

Collaborative work environment

Job summary

Tachyum in Sunnyvale, CA, is seeking engineers to work on a high-performance L2 Cache unit for AI processing elements within state-of-the-art hardware platforms.

The role focuses on processor pipelines, cache architectures, and low-power design across multicore SoCs using Verilog/SystemVerilog. Experience with ARM/x86 cores and scripting is a plus. Tachyum offers an international environment and opportunities for career progression.

Qualifications

• Experience with high speed processor pipelines/ASICs/SoCs and multi-core designs.
• Strong understanding of computer architecture and cache coherency.
• Experience with cache controller designs, cache hierarchy, and coherency protocols.
• Logic design experience with deep submicron technologies and low power techniques.
• Proficiency in Verilog / SystemVerilog, Synthesis, STA, CDC, Lint.
• Knowledge of ARM and x86 multicore processor designs is a plus.
• Knowledge of C and scripting languages (Perl / shell / Python / awk) is a plus.

Responsibilities

• Working on high performance L2 Cache unit for AI processing elements.

Skills

Processor pipelines

Computer architecture

Cache coherency

Low power design

Verilog / SystemVerilog

ARM/x86 multicore

C and scripting

Job description

Tachyum in Sunnyvale, CA, is seeking engineers to work on a high-performance L2 Cache unit for AI processing elements within state-of-the-art hardware platforms.

The role focuses on processor pipelines, cache architectures, and low-power design across multicore SoCs using Verilog/SystemVerilog. Experience with ARM/x86 cores and scripting is a plus. Tachyum offers an international environment and opportunities for career progression.