Senior Design Engineer – AI SoC Development

Jobtailor; California (MO); On-site; USD 140,000 - 190,000; Full time

Job summary

Jobtailor seeks an experienced RTL design engineer to contribute to complex SoC developments, integrating IP blocks and subsystems into full chip designs. The role involves architecture definition, quality checks, and close collaboration with verification teams to ensure robust RTL and timing converge.

The ideal candidate has 7+ years in RTL for ASIC/SoC, deep knowledge of bus protocols like AXI/AHB, and strong scripting skills (Python/TCL) for design automation.

Qualifications

• 7+ years of RTL design and implementation for ASIC/SoC development.
• Experience solving clock domain crossings and timing closure.
• Hands-on SoC system integration and multicore CPU subsystem design.
• Strong knowledge of AXI, AHB, and embedded processor architectures.
• Proficiency in scripting (Python, TCL) for automation.
• Familiarity with industry-standard EDA tools and FPGA prototyping.

Responsibilities

• Develop RTL, RTL coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete component designs.
• Define architecture and microarchitecture features of the blocks and perform quality checks across RTL to timing/power convergence.
• Write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation.
• Collaborate with verification teams to ensure RTL tests pass and address failures.
• Follow secure development practices and validate IPs at the SoC level, driving QA for smooth IP/SoC handoff.

Skills

RTL design

ASIC/SoC

Clock domain crossing

Power optimization

Timing closure

SoC integration

Multicore CPU

AXI bus

Embedded processors

High-speed design

Low-power design

Python scripting

TCL scripting

Education

BS or MS in Electrical/Computer Engineering or CS

Tools

VCS

Questa

Xcelium

Spyglass

Vivado

Quartus II

Job description

Responsibilities

• Develop logic design, register transfer level (RTL) coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete component designs.
• Participate in defining architecture and microarchitecture features of the blocks being designed and perform quality checks across various logic design aspects ranging from RTL to timing/power convergence.
• Apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation.
• Work closely with verification teams, review verification plans and implementation to ensure design features are verified correctly, resolving and implementing corrective measures for failing RTL tests.
• Follow secure development practices to address security threat models and security objectives within the design, work with IP providers to integrate and validate IPs at the SoC level, and drive quality assurance compliance for smooth IP/SoC handoff.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 7+ years of experience in RTL design and implementation for ASIC/SoC development.
• Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure.
• Hands‑on experience with SoC system integration and multicore CPU subsystem design.
• Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
• Expertise in high-speed and low-power design techniques.
• Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization.
• Familiarity with industry standard EDA tools, including simulators (VCS, Questa, Xcelium), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).
• Ability to thrive in a dynamic environment with evolving requirements.