Lead SoC Design Engineer

jobr.pro; Los Altos (CA); On-site; USD 190,000 - 230,000; Full time

Job summary

jobr.pro, a stealth startup building a next-generation edge computing platform, seeks a Lead SoC Design Engineer in California to drive microarchitecture and RTL design, tackling aggressive PPA targets in collaboration with verification and software teams.

You will own critical subsystems, manage timing and power constraints, and help shepherd silicon from RTL to physical design. This senior role requires deep ASIC know-how and leadership.

Qualifications

• 10+ years of experience in developing complex ASICs in advanced nodes.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
• Deep knowledge of AMBA AXI/AXI-S/APB on-chip interconnect protocols.
• Experience with Verilog, SystemVerilog, and SystemVerilog Assertions (SVA).
• Proficiency with writing and debugging SDC timing constraints (multi-cycle paths, false paths, clock domain crossing).
• Experience with ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.
• Experience designing with multiple power domains and UPF.

Responsibilities

• Author detailed microarchitecture documents and drive reviews with software, architecture and verification teams.
• Drive performance/power tradeoffs to hit aggressive PPA targets.
• Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.
• Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure design can be taken through physical design to meet frequency and power requirements.

Skills

Verilog/SystemVerilog

SVA (SystemVerilog Assertions)

SDC timing constraints

AMBA AXI/AXI-S/APB

ASIC CAD tools (simulation, synthesis,

power estimation

Power domains and UPF

Education

Bachelor's or Master’s in Electrical/Computer Engineering

Job description

Summary

We’re a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. By integrating flagship compute IP into an industry-leading design, we are building the optimized silicon foundation for our software platform from the ground up.

We’re building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop the microarchitecture, own the critical tradeoffs required to hit aggressive PPA targets, and spearhead the implementation of key subsystems.

Responsibilities

• Microarchitecture: Author detailed microarchitecture documents and drive reviews with software, architecture and verification teams.
• Drive PPA targets: Since we are developing a power-sensitive client product, you will drive performance/power tradeoffs using a data-driven approach to hit aggressive targets.
• Partner with verification team: Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.
• RTL design: Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure that the design can be taken through physical design to meet frequency and power requirements.

Minimum Requirements

• 10+ years of experience in developing complex ASICs in advanced nodes.
• Bachelor\'s or Master\'s degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• Deep knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB).
• Experienced with Verilog, SystemVerilog, SystemVerilog Assertions (SVA).
• Proficiency in writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints.
• Experience with industry-standard ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.
• Experience designing with multiple power domains and UPF.

Preferred Qualifications

• Experience with commercial IP integration, ranging from high-speed interfaces (UCIe, DDR) to processing subsystems (CPU, GPU).
• Experience working directly with Arm cores and subsystems.