Senior DDR5/DDR6 Analog Engineering Lead

Renesas Electronics Corporation; Johns Creek (GA); On-site; USD 150,000 - 210,000; Full time

Job summary

Renesas Electronics Corporation seeks a Senior Analog Engineering Manager to lead DDR5/DDR6 PHY development for advanced SoCs. You will oversee architecture through silicon bring-up, guiding high-speed memory interfaces with a strong emphasis on timing, power, and signal integrity.

You will mentor a team of analog and mixed-signal designers, drive production readiness, and collaborate across SoC, package, PCB, and validation groups to shape the DDR6 roadmap.

Qualifications

• 12+ years of analog/mixed-signal IC design with deep focus on high-speed memory interfaces.
• 5+ years of people-management and technical leadership experience.
• Experience delivering DDR5 PHYs or transitioning designs to DDR5.

Responsibilities

• Lead architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.
• Provide technical oversight for high-speed analog/mixed-signal blocks (TX/RX datapaths, equalization, training circuits).
• Drive timing, jitter, noise, SI/PI, and PVT robustness for high data-rate operation; ensure JEDEC DDR5 compliance.
• Lead post-silicon bring-up, characterization, debug, and yield improvement with lab and customer-system correlation.
• Build, mentor, and scale a team of analog and mixed-signal designers; set direction and development plans.
• Own DDR5/DDR6 PHY execution with cross-functional collaboration across SoC, package, PCB, validation, and customers.
• Establish design methodologies, improve simulation accuracy, and drive roadmap for DDR5 sustenance and DDR6 evolution.

Skills

High-speed IO design

Signal integrity

PLL/DLL clocking

Mixed-signal verification

Silicon validation

CMOS IO considerations

Education

Electrical Engineering degree (PhD preferred)

Job description

Renesas Electronics Corporation seeks a Senior Analog Engineering Manager to lead DDR5/DDR6 PHY development for advanced SoCs. You will oversee architecture through silicon bring-up, guiding high-speed memory interfaces with a strong emphasis on timing, power, and signal integrity.

You will mentor a team of analog and mixed-signal designers, drive production readiness, and collaborate across SoC, package, PCB, and validation groups to shape the DDR6 roadmap.