ASIC Verification Engineer — Equity & Benefits

NVIDIA Corporation; Austin (TX); On-site; USD 116,000 - 219,000; Full time

Job summary

NVIDIA in Austin, TX is seeking an entry-level ASIC Verification Engineer to impact system-level IP verification. You’ll verify RTL using SystemVerilog, UVM, and OOP-based scripting, and contribute to robust verification methodologies across unit, sub-system, and SOC levels.

You will design and maintain unit/sub-system verification environments, create UVM components and scoreboards, run regressions, automate builds, and collaborate with architects, designers, and software engineers to hit DV

Qualifications

• MS or higher in Computer or Electrical Engineering (or equivalent).
• Experience in SystemVerilog, UVM, and OOP-based programming.
• Strong coding skills in Python or other scripting languages.
• Strong understanding of RTL design (Verilog).
• Good knowledge of computer architecture fundamentals.
• Familiarity with verification tools such as VCS or Verdi.

Responsibilities

• Design and maintain the unit level/sub-system Verification environment.
• Understand architecture specifications, develop and carry out the test plan to verify the design.
• Create the UVM components, sequences, tests and scoreboards.
• Sign off on the verification efforts with high quality code and coverage.
• Launch regressions, resolve issues, and progress toward DV milestones.
• Automate manual steps for launching build, regression, and triages.
• Collaborate with architects, designers, and software engineers to meet project goals.
• Proactively improve testbenches using the latest techniques.

Skills

SystemVerilog

UVM

OOP-based programming

Python scripting

Education

MS or higher in Computer or Electrical Engineering

Tools

VCS

Verdi

Job description

NVIDIA in Austin, TX is seeking an entry-level ASIC Verification Engineer to impact system-level IP verification. You’ll verify RTL using SystemVerilog, UVM, and OOP-based scripting, and contribute to robust verification methodologies across unit, sub-system, and SOC levels.

You will design and maintain unit/sub-system verification environments, create UVM components and scoreboards, run regressions, automate builds, and collaborate with architects, designers, and software engineers to hit DV