Senior SoC Verification Engineer: Next‑Gen AI Chips & Equity

NVIDIA; Austin (TX); On-site; USD 168,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an exceptional Senior SoC ASIC Verification Engineer to confirm the functionality of the world’s most powerful AI-enabled SoCs. Based in Austin, TX, you will join a world-class team shaping the verification strategy for next‑generation devices powering autonomous vehicles, gaming systems, and embedded platforms.

You’ll define verification plans, build scalable testbenches, and collaborate with architects, RTL, FPGA and emulation teams to ensure quality and correctness across

Qualifications

• Bachelor's Degree in EE, CS, CE, or equivalent experience.
• 5+ years of relevant experience in ASIC DV.
• Outstanding analytical and problem-solving skills.
• Experience in crafting testbenches and methodologies for large and complex chips.
• Deep understanding of verification concepts.
• Familiarity with verification challenges in large-scale builds.
• Solid understanding of basic concepts of CPU or SoC architecture.
• Experience with verification of SoCs with embedded processors or CPU verification.

Responsibilities

• Define verification strategies and complete plans at the full chip level.
• Build and continuously reform verification infrastructure and methodologies to meet the demands of next-generation SoCs.
• Collaborate with architects, RTL designers, FPGA, and emulation engineers to ensure verification requirements are met for each project.

Skills

C++

SystemVerilog

UVM

Object-Oriented Programming

Education

Bachelor's in EE/CS/CE

Job description

NVIDIA is seeking an exceptional Senior SoC ASIC Verification Engineer to confirm the functionality of the world’s most powerful AI-enabled SoCs. Based in Austin, TX, you will join a world-class team shaping the verification strategy for next‑generation devices powering autonomous vehicles, gaming systems, and embedded platforms.

You’ll define verification plans, build scalable testbenches, and collaborate with architects, RTL, FPGA and emulation teams to ensure quality and correctness across