Senior Fabric & Interconnect Verification Engineer (SoC/NoC)

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA Corporation in Santa Clara, CA seeks a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions. You will develop test plans in UVM, build constrained-random/SystemVerilog benches, and collaborate across architecture, software, design, and post-silicon teams to ensure first-time-right verification for fabric and interconnect subsystems.

Requirements include SystemVerilog/UVM expertise, strong knowledge of interconnect protocols (AXI/CHI), and scripting

Qualifications

• Bachelor's or master's in Computer Engineering or Electrical Engineering (or related field).
• 6+ years in ASIC verification, with fabric/interconnect or NoC exp.
• Strong SystemVerilog and UVM knowledge.
• Familiar with interconnect protocols (AXI/CHI) and NoC architectures.

Responsibilities

• Verify ASIC fabric/interconnect IP blocks and full chip integration (DMA, routing, arbitration, ordering, flow control, protocol compliance).
• Develop and implement test plans for fabric/interconnect verification in UVM environments (IP- and system-level).
• Create constrained-random and directed SystemVerilog testbenches for interconnect fabrics and NoC topologies.
• Collaborate with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams for robust verification plans.
• Lead silicon and platform verification strategies for fabric/interconnect subsystems.

Skills

SystemVerilog

UVM

Python

Perl

TCL

NoC

AXI/CHI

Education

B.S./M.S. in Computer/ Electrical Engineering

Tools

Palladium

Veloce

Job description

NVIDIA Corporation in Santa Clara, CA seeks a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions. You will develop test plans in UVM, build constrained-random/SystemVerilog benches, and collaborate across architecture, software, design, and post-silicon teams to ensure first-time-right verification for fabric and interconnect subsystems.

Requirements include SystemVerilog/UVM expertise, strong knowledge of interconnect protocols (AXI/CHI), and scripting