Senior Custom Logic & STA Engineer (Analog/Mixed-Signal)

Apple Inc.; Sunnyvale (CA); Hybrid; USD 129,000 - 225,000; Full time

Benefits offered by this job

Stock options

Employee Stock Purchase Plan

Comprehensive medical and dental

Retirement benefits

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. is seeking a self-motivated Custom Logic Design and STA engineer for the Analog/Mixed Signal Design team in Sunnyvale, CA.

You will perform timing analysis on custom circuits and develop custom logic in analog/mixed-signal designs, working with cross-functional teams to ensure timing closure and performance. Responsibilities include timing closure ownership, developing STA constraints, and collaborating with RTL and verification teams to deliver robust silicon IPs.

Qualifications

• Bachelor’s degree in engineering or related field.
• Strong understanding of setup/hold, path delays and timing constraints.
• Experience in timing verification for high-speed design (SerDes/ADC).
• Deep knowledge of mixed-signal design techniques and transistor-level behavior.
• Proven track record delivering silicon IPs with design and verification.

Responsibilities

• Own timing closure for custom design across the project cycle.
• Develop and implement STA constraints from specifications.
• Perform block- and chip-level static timing and noise analysis.
• Design and characterize transistor- and gate-level mixed-signal circuits.
• Collaborate with RTL and CAD teams on timing changes and robust designs.
• Assist design verification and DFT to debug issues.
• Support CAD in timing verification methodologies and flows.

Skills

Timing analysis

SerDes

ADC

Mixed-signal design

Timing closure

STA tools

SPICE modeling

Scripting (Python)

Education

Bachelor's degree

Master’s degree

Tools

NanoTime

PrimeTime

Tempus

Job description

Apple Inc. is seeking a self-motivated Custom Logic Design and STA engineer for the Analog/Mixed Signal Design team in Sunnyvale, CA.

You will perform timing analysis on custom circuits and develop custom logic in analog/mixed-signal designs, working with cross-functional teams to ensure timing closure and performance. Responsibilities include timing closure ownership, developing STA constraints, and collaborating with RTL and verification teams to deliver robust silicon IPs.