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Apple, Inc. is seeking an ASIC STA Engineer in Beaverton, Oregon to own full chip and block timing closure and develop timing methodologies for high-end mobile SOCs.
You will collaborate with multi-functional teams to resolve complex timing issues, generate timing constraints, and ensure high-quality IP deliverables in deep sub-micron processes. A strong foundation in digital design and scripting is essential.
Apple, Inc. is seeking an ASIC STA Engineer in Beaverton, Oregon to own full chip and block timing closure and develop timing methodologies for high-end mobile SOCs.
You will collaborate with multi-functional teams to resolve complex timing issues, generate timing constraints, and ensure high-quality IP deliverables in deep sub-micron processes. A strong foundation in digital design and scripting is essential.