Senior Custom ASIC Engineering Lead

Broadcom; Irvine (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grant

401(k) matching

Employee Stock Purchase Program

Job summary

Broadcom is seeking a senior engineer to lead external and internal cross-functional teams in physical design, STA, DFT, and packaging, bringing extensive tape-out experience and expertise in addressing EDA reports.

You will guide customer teams working on AI, HPC, networking and storage chips, manage programs end-to-end, and advise on best practices while coordinating with marketing, sales, legal and compliance teams.

Qualifications

• Multiple tape-outs in advanced technology nodes.
• Analyze PPA tradeoffs among library components and architectures.
• Knowledge of low power design and power management.
• Hands-on experience in physical design, STA, EDA tools, design flows, logic simulation, test and packaging.
• Programming in TCL, shell and scripting languages.

Responsibilities

• Manage external customer ASIC programs from inception to finish, including RFQs, technology/IP collaterals, design, test, packaging, fabrication, bring-up and production.
• Advise customers on best practices in EDA flows and design methodologies; host Q&A sessions.
• Assess risks to design quality and schedule; work with cross-functional teams to mitigate.
• Execute physical design flows to verify tape-in netlists meet Broadcom’s tape-out standards.
• Keep abreast of Broadcom IPs, technology and end-user applications.
• Participate in discussions about chips with marketing, sales, legal and compliance teams.
• Be a team player and assist other teams as needed.

Skills

Tape-out experience

PPA tradeoffs

Low power design

Physical design

STA

Verilog RTL

Scripting (TCL/Shell)

Education

Bachelor's degree + 12+ years OR Master's + 10+ years

Tools

EDA tools

Job description

Job Description:

Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, and packaging? Have you taped out so many chips that you can identify potential design problems hidden in EDA reports, advise design teams on how to fix them, and then publish an application note about avoiding them in future? Do you love technical-deep-dive with engineers and providing an eagle’s eye summary to management? If this is your engineering profile and you are looking for a challenge, then we have one for you.

Broadcom develops critical Infrastructure chips that enable a variety of Customers to produce ASICs in almost all major segments of the Semiconductor industry, including AI. Our ASIC Products Division is looking for a senior engineer to guide customer teams designing challenging chips in areas such as AI, HPC, networking and storage. This is an immensely responsible position, and an opportunity to push the frontiers of technology by working with cross-functional teams inside and outside of Broadcom.

As a valued member of this team, you will be required to do the following:

• Manage external customer ASIC programs from inception to finish, including RFQs, technology and IP collaterals, design, test, packaging, fabrication, bring-up and production

• Advise customers on best practices in EDA, flows and design methodologies, and by organizing Q&A sessions with Broadcom technology experts

• See ahead, plan ahead, work ahead. Proactively assess potential risks to the design quality and project schedule, then work with cross-functional teams to prepare and execute risk mitigation actions

• Execute physical design flows to check that incoming customer tape-in netlists meet Broadcom’s stringent tape-out quality standards

• Motivate and drive yourself to stay abreast of developments in Broadcom IPs, technology and end user applications

• Participate in discussions about your chips with marketing, sales, legal and regulatory compliance teams

• Be a consummate team player and assist other teams in need

You must have these proven skills to qualify for this position:

• Multiple tape-outs in advanced technology nodes

• Analyze PPA tradeoffs involved amongst various library components, and architectures

• Knowledgeable in low power design and power management

• Hands-on experience in physical design and STA, EDA tools, design flows for physical design, logic simulation, test, and packaging

• Programming in TCL, shell and scripting languages

Following skills are nice to have:

• Exposure to SERDES communications protocols.

• Logic design, chip architecture, microarchitecture, Verilog RTL coding Front-end logic design verification, DRC, logic synthesis

• Knowledge of DFT methods including scan, memory BIST and repair

Education and Experience Requirements:

• Bachelors degree and 12+ years of related experience; or Masters degree and 10+ years of related experience

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is$143,800 - $230,000.

As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.