ASIC Implementation Engineer PD

Broadcom Inc.; San Jose (CA); On-site; USD 121,900 - 195,000; Full time

Job summary

Broadcom Inc. is seeking an ASIC top-level floorplan Physical Design Engineer to join the ASIC Products Division in San Jose.

You will own floorplanning, clocking and I/O planning for top-level partitions, collaborating with design, package and methodology teams to deliver silicon tape-out. The role requires deep experience in die size estimation, partitioning and DRC/LVS resolution for advanced nodes, plus scripting skills (Python/Tcl/Perl) and hands-on use of EDA tools.

Qualifications

• Bachelor’s degree plus 8+ years in top-level floorplanning with die size estimate, partitioning, clocking and pin planning
• Or Master’s degree with 6+ years in top-level floorplanning with die size estimate, partitioning, clocking and pin planning
• Experience with Switch Fabric, Arbiter, High-Speed DDR, SerDes, HBM, D2D I/O, chiplet, etc.
• Experience resolving chip-level DRC/LVS/EMIR issues for advanced nodes
• Proven track record with bump planning, RDL implementation, and multi-voltage domain designs
• Experience with hierarchical floorplanning, power grid design, structured clocks, top-level pipeline planning, custom routes and bump planning
• Experience collaborating with design, package and methodology teams during development
• Must work in person at our San Jose site – no remote work option

Responsibilities

• Own chip floor planning, partition creation, clock tree and delivery of top-level partitions
• Resolve physical design issues related to chip integration and assembly
• Manage all cross-functional interactions related to top-level floorplanning, I/O and bump planning with package team
• Develop and improve floorplan implementation methodologies using both industry and internal tools
• Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specifications

Skills

Floorplanning

Clocking

Pin planning

Python

Tcl

Perl

EDA tools

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

EDA tools

Job description

Job Description

Broadcom is searching for an ASIC top‑level floorplan Physical Design Engineer to join the ASIC Products Division. This position involves working with the latest technology to continue driving next‑generation Artificial Intelligence and PCIe Switch Products. More specifically, this role requires in‑depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape‑out.

Responsibilities

• Own chip floor planning, partition creation, clock tree and delivery of top‑level partitions


• Resolve physical design issues related to chip integration and assembly


• Manage all cross‑functional interactions related to top‑level floorplanning, I/O and bump planning with package team


• Develop and improve floorplan implementation methodologies using both industry and internal tools


• Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specifications

Preferred Qualifications

• Bachelor’s degree in Electrical Engineering and 8+ years of experience in top‑level floorplanning with a focus on die size estimate, partitioning, clocking and pin planning


• Or Master’s degree in Electrical Engineering and 6+ years of experience in top‑level floorplanning with a focus on die size estimate, partitioning, clocking and pin planning


• Experience working on various technologies (Switch Fabric, Arbiter, High‑Speed DDR, SerDes, HBM, D2D I/O, chiplet, etc.)


• Experience in resolving chip‑level DRC/LVS/EMIR issues for advanced nodes


• Proven track record with bump planning, RDL implementation, and multi‑voltage domain designs


• Experience with hierarchical floorplanning, power grid design, structured clocks, top‑level pipeline planning, custom routes and bump planning


• Experience collaborating with design, package and methodology teams during the development phase


• Experience in scripting languages such as Python, Tcl or Perl, and in EDA tools


• Must work in person at our San Jose site – no remote work option

Compensation and Benefits

The annual base salary range for this position is USD 121,900 to USD 195,000. As a valued member of the team, you will be eligible for a discretionary annual bonus and the opportunity to receive a competitive new‑hire equity grant, as well as annual equity awards, linking your success directly to the company’s growth. All are subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: medical, dental and vision plans; 401(k) participation with company matching; Employee Stock Purchase Program (ESPP); Employee Assistance Program (EAP); company‑paid holidays; paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Equal Opportunity Employer

Broadcom is proud to be an equal‑opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by federal, state or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.