Senior CPU Emulation Architect

Socket.dev; Austin (TX); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Bonus target 15%

Equity and benefits

Job summary

Google is seeking a senior RTL engineer to join a team developing custom silicon solutions powering the company\'s direct-to-consumer products. You\'ll contribute to advanced emulation and FPGA prototyping efforts across industry-standard platforms, shaping performance and efficiency.

You will architect RTL partitions, drive pre-silicon verification, and collaborate with DV and silicon design teams to deliver scalable hardware solutions.

Qualifications

• Bachelor's degree or equivalent practical experience in a relevant field.
• 8+ years of experience with industry-standard emulation or FPGA prototyping platforms.
• Experience with RTL design using Verilog or SystemVerilog.
• Experience scripting or developing automation workflows in Python, Perl, TCL, or Makefiles.

Responsibilities

• Architect and drive RTL partitioning, FPGA synthesis, and validation strategies for emulation platforms.
• Define and execute test suites, benchmarks, and workloads for pre-silicon verification and system-level validation.
• Lead debugging methodologies to rapidly isolate and resolve complex functional failures in large-scale designs.
• Optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization in emulation farms.
• Architect automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline CI.

Skills

RTL design Verilog/SystemVerilog

Automation scripting

Emulation/FPGA prototyping

Education

Bachelor's degree in EE/CE/CS or related field

Tools

Industry-standard emulation platforms

Job description

Google is seeking a senior RTL engineer to join a team developing custom silicon solutions powering the company\'s direct-to-consumer products. You\'ll contribute to advanced emulation and FPGA prototyping efforts across industry-standard platforms, shaping performance and efficiency.

You will architect RTL partitions, drive pre-silicon verification, and collaborate with DV and silicon design teams to deliver scalable hardware solutions.