Senior CPU RTL Design Engineer

Google; Mountain View (CA); On-site; USD 163,000 - 237,000; Full time

Job summary

Google in Mountain View, CA, USA seeks a Senior CPU RTL Design Engineer to advance CPU cache subsystems with RTL focus. You will collaborate across performance, architecture, and software teams to evaluate trade-offs and optimize microarchitectures for future CPUs.

Requires a Bachelor's in a related field and 8 years' experience with SystemVerilog, Lint, UPF, and CPU cache designs. Google offers a strong compensation package and equity as part of total rewards.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
• Experience with RTL language (e.g. System Verilog) and related design processes (Lint, UPF).

Responsibilities

• Engage in developing CPU cache subsystems, focusing on RTL design and microarchitecture for future CPU generations.
• Collaborate with performance, architecture, and software teams to evaluate trade-offs and suggest microarchitectural improvements that boost performance.
• Deliver high-quality designs on time while articulating the advantages and disadvantages of various microarchitecture updates.
• Partner with verification, power, and physical design teams to ensure designs meet area, power, and frequency targets.
• Optimize cache unit design and coordinate with other design units within CPU subsystems to achieve excellent power, performance, and area.

Skills

RTL design

SystemVerilog

Lint

UPF

CPU cache subsystems

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Senior CPU RTL Design Engineer

Google

Mountain View, CA, USA

Mid

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
• Experience with RTL language (e.g. System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:

• PhD in Electrical Engineering or Computer Science, or a related field.
• Experience leading front-end design for modern processor components or AI accelerators.
• Experience with ARM Instruction Set Architecture or CPU subsystems.
• Experience with SoC design, architecture, and integration.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Engage in developing CPU cache subsystems, focusing on RTL design and microarchitecture for future CPU generations.
• Collaborate with performance, architecture, and software teams to evaluate trade-offs and suggest microarchitectural improvements that boost performance.
• Deliver high-quality designs on time while articulating the advantages and disadvantages of various microarchitecture updates.
• Partner with verification, power, and physical design teams to ensure designs meet area, power, and frequency targets.
• Optimize cache unit design and coordinate with other design units within CPU subsystems to achieve excellent power, performance, and area.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.