Principal CPU Physical Design Engineer (San Diego, CA)

Qualcomm; San Diego (CA); On-site; USD 211,900 - 317,900; Full time

Benefits offered by this job

Annual discretionary bonus

RSU grants

Comprehensive benefits package

Job summary

Qualcomm is seeking a CPU Physical Design expert to drive the next generation of computing in San Diego. In this key role, you will own critical CPU implementation tasks, optimizing performance and efficiency while collaborating with teams on forward-thinking design strategies. The position demands over 10 years of ASIC/SoC experience and expertise with RTL-to-GDSII processes.

Enjoy working on cutting-edge technology with opportunities for career advancement and competitive compensation, including bonuses and RSU grants.

Qualifications

• 10+ years of experience in ASIC/SoC Physical Design.
• Strong experience with RTL-to-GDSII implementation.
• Experience in timing closure and power optimization.

Responsibilities

• Own critical portions of CPU implementation from RTL to GDS.
• Drive optimization for high-frequency, complex CPU subsystems.
• Partner with teams to co-optimize design for physical implementation.

Skills

ASIC/SoC Physical Design

RTL-to-GDSII implementation

Timing closure

Power optimization

Scripting skills (TCL, Python)

Education

Bachelor’s in Electrical/Computer Engineering

Master’s in Electrical/Computer Engineering

PhD in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Job description

Company: Qualcomm Technologies, Inc.

General Summary

Drive the Silicon That Powers the Next Generation of Computing.
We’re looking for a CPU Physical Design expert to push the limits of performance, power efficiency, and scalability in next‑generation CPU designs. In this role, you will work on industry‑leading CPU cores at advanced nodes, solving some of the most challenging problems in modern semiconductor design. This is a high‑impact role with broad visibility—where your contributions directly influence architecture trade‑offs, implementation strategies, and silicon success.

What You’ll Do

• Own critical portions of CPU implementation from RTL to GDS, with a focus on PPA convergence and design quality
• Drive timing, power, and area optimization for high‑frequency, complex CPU subsystems
• Partner with Architecture, RTL, and Circuit teams to co‑optimize design for physical implementation
• Solve hard silicon problems: timing closure, congestion, variability, EM/IR, and power integrity
• Develop and deploy methodologies, flows, and automation to improve scalability and QoR across projects
• Influence and collaborate with EDA vendors and CAD teams to push tool capabilities
• Contribute to next‑gen design strategies for advanced nodes
• Mentor junior engineers and help raise the technical bar of the team

Required Skill/Experience

• 10+ years of experience in ASIC/SoC Physical Design
• Strong experience with full RTL‑to‑GDSII implementation (synthesis, place & route, STA, signoff)
• Experience in timing closure and power optimization
• Scripting skills (TCL, Python, or similar)

Preferred Qualifications

• Experience working on CPU cores or other high‑performance designs
• Expertise in advanced nodes (7nm, 5nm, 3nm or below)
• Strong understanding of PPA trade‑offs and CPU‑specific design challenges
• Hands‑on experience with industry‑standard tools (Synopsys/Cadence)
• Experience developing or influencing design methodologies
• Strong data‑driven debug and analytical skills

Why You’ll Love This Role

• Work on cutting‑edge CPU architectures used in millions of devices worldwide
• Solve deep technical challenges at advanced nodes
• Have real influence across architecture and silicon implementation
• Collaborate with top‑tier engineers across disciplines
• Grow into technical leadership roles (Staff / Sr Staff / Principal)
• Be part of a high‑impact team in San Diego

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Pay Range and Other Compensation & Benefits

$211,900.00 - $317,900.00. Includes competitive annual discretionary bonus and RSU grants. Additional benefits package supports success at work, home, and play.

EEO Statement

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.