SoC Power Architect, Devices and Services, Silicon

Google; Mountain View (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google seeks a highly skilled power management engineer to help define power requirements for Tensor mobile SoCs and optimize Power-Performance-Area under peak current and thermal constraints. You will work closely with design, architecture and verification teams to deliver robust, energy-efficient hardware solutions.

You will lead cross-functional efforts to drive power KPIs across major SoC IPs, propose optimizations from concept to mass production, and report progress to executive leadership,

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 10 years of experience in power management or low power design/methodology.
• Experience with low power architecture and power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, DVFS, AVS).
• Experience with full product delivery cycle (definition, architecture, design and implementation, testing, productization).

Responsibilities

• Lead the definition of power requirements for Tensor mobile SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
• Own and drive cross-functional teams to deliver on competitive power KPIs for one or more major SoC IPs such as memory subsystem, multimedia subsystem, etc.
• Propose and drive power optimizations throughout the design process from concept to mass productization.
• Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
• Represent the status of SoC power to executive leadership team.

Skills

Power management

Low power design/methodology

DVFS/AVS

Clock gating / power gating

System-level product delivery

Education

Bachelor's degree in Electrical Engineering or equivalent practical experience

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 10 years of experience in power management or low power design/methodology.
• Experience with low power architecture and power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS)).
• Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).

Preferred qualifications:

• Master's degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.
• Experience with system-level power modeling, optimizations and analysis for one or more major SoC subsystems such as memory path, multimedia, etc.
• Excellent written and verbal communication skills, with the ability to work with cross-functional teams to drive consensus and influence product decisions.
• Exceptional leadership, organizational, communication, and persuasion skills.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Lead the definition of power requirements for Tensor mobile SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
• Own and drive cross-functional teams to deliver on competitive power key performance indicator (KPIs) for one or more major SoC IPs such as memory subsystem, multimedia subsystem, etc.
• Propose and drive power optimizations throughout the design process from concept to mass productization.
• Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
• Represent the status of SoC power to executive leadership team.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .