Senior CPU RTL Design Engineer

Google; Portland (OR); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking an experienced IC engineer to advance CPU cache subsystems with a focus on RTL design and microarchitecture for the next generation of processors. You will collaborate with performance, architecture, and software teams to evaluate trade-offs and drive improvements.

Be part of a team that combines hardware and software to deliver high-performance, efficient silicon. The role involves verification and coordinating with power and area targets across CPU subsystems.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
• Experience with RTL language (e.g. System Verilog) and related design processes (e.g., Lint, UPF).

Responsibilities

• Engage in developing CPU cache subsystems, focusing on RTL design and microarchitecture for future CPU generations.
• Collaborate with performance, architecture, and software teams to evaluate trade-offs and suggest microarchitectural improvements that boost performance.
• Deliver high-quality designs on time while articulating the advantages and disadvantages of various microarchitecture updates.
• Partner with verification, power, and physical design teams to ensure designs meet area, power, and frequency targets.
• Optimize cache unit design and coordinate with other design units within CPU subsystems to achieve excellent power, performance, and area.

Skills

Cache subsystem design

RTL design

CPU microarchitecture

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

SystemVerilog

Lint/UPF

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Portland, OR, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
• Experience with RTL language (e.g. System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:

• PhD in Electrical Engineering or Computer Science, or a related field.
• Experience leading front-end design for modern processor components or AI accelerators.
• Experience with ARM Instruction Set Architecture or CPU subsystems.
• Experience with SoC design, architecture, and integration.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Engage in developing CPU cache subsystems, focusing on RTL design and microarchitecture for future CPU generations.
• Collaborate with performance, architecture, and software teams to evaluate trade-offs and suggest microarchitectural improvements that boost performance.
• Deliver high-quality designs on time while articulating the advantages and disadvantages of various microarchitecture updates.
• Partner with verification, power, and physical design teams to ensure designs meet area, power, and frequency targets.
• Optimize cache unit design and coordinate with other design units within CPU subsystems to achieve excellent power, performance, and area.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .