Senior CPU Library Design Engineer — Custom Cells & PPA

NUVACORE; Austin (TX); Vor Ort; USD 180.000 - 280.000; Vollzeit

Zusammenfassung

NUVACORE is building a ground‑up, high performance, low‑power CPU for next‑generation compute workloads. You will design library cells and own IP closure from schematic to layout, interfacing with foundry and CAD teams to optimize PPA on advanced CMOS nodes.

You will contribute to defining flows, automation, and QA processes, while working with DFT and timing models. This senior role requires strong collaboration and deep transistor‑level expertise.

Qualifikationen

• BS or MS in electrical engineering or related field.
• 12+ years of standard cell and/or memory circuit design experience.
• Hands-on transistor‑level design with latches/FFs and custom logic at advanced CMOS nodes.
• Proficient with industry‑standard EDA tools for schematic, layout, extraction and characterization.
• Experience giving feedback to foundry partners to improve PPA and yield.
• Familiar with STA and Liberty/CCS models for timing/power in Functional and DFT modes.
• Strong communication and collaboration skills with foundry, CAD, and physical design teams.

Aufgaben

• Design and characterize library cells including flip-flops, clock-gating cells, level shifters, and AOI cells to optimize PPA.
• Own end-to-end library IP closure: schematic and layout through DRC/LVS/antenna and characterization.
• Partner with Foundry/PDK, CAD, Physical Design, and DFT teams to benchmark process tech and validate IP on test chips.
• Define and drive adoption of tools, flows, and methodology to raise design efficiency and set team-wide practices.

Kenntnisse

Library cells

Transistor‑level design

CDSL/CMOS timing

EDA tool proficiency

STA/Liberty models

Communication & collaboration

Ausbildung

BS or MS in Electrical Engineering

Tools

Schematic capture

Layout editors

Parasitic extraction

DC/AC characterization tools

Jobbeschreibung

NUVACORE is building a ground‑up, high performance, low‑power CPU for next‑generation compute workloads. You will design library cells and own IP closure from schematic to layout, interfacing with foundry and CAD teams to optimize PPA on advanced CMOS nodes.

You will contribute to defining flows, automation, and QA processes, while working with DFT and timing models. This senior role requires strong collaboration and deep transistor‑level expertise.